linux-kernel - Re: [PATCHv1 18/19] arm64: dts: rockchip: Add base DT for rk3588 SoC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20220425181407.lknemxqooz7yidcz@mercury.elektranox.org>
Date:   Mon, 25 Apr 2022 20:14:07 +0200
From:   Sebastian Reichel <sebastian.reichel@...labora.com>
To:     Robin Murphy <robin.murphy@....com>
Cc:     Heiko Stuebner <heiko@...ech.de>, Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Bartosz Golaszewski <brgl@...ev.pl>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
        linux-mmc@...r.kernel.org, linux-gpio@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, kernel@...ts.collabora.co.uk,
        Kever Yang <kever.yang@...k-chips.com>, kernel@...labora.com,
        Yifeng Zhao <yifeng.zhao@...k-chips.com>,
        Elaine Zhang <zhangqing@...k-chips.com>,
        Sugar Zhang <sugar.zhang@...k-chips.com>
Subject: Re: [PATCHv1 18/19] arm64: dts: rockchip: Add base DT for rk3588 SoC

Hi,

Thanks for having a look.

On Fri, Apr 22, 2022 at 07:16:13PM +0100, Robin Murphy wrote:
> On 2022-04-22 18:09, Sebastian Reichel wrote:
> > ...
> > +		cpu_l0: cpu@0 {
> > +			device_type = "cpu";
> > +			compatible = "arm,cortex-a55";
> > +			reg = <0x0>;
> > +			enable-method = "psci";
> > +			capacity-dmips-mhz = <530>;
> > +			clocks = <&scmi_clk SCMI_CLK_CPUL>;
> > +			i-cache-size = <32768>;
> > +			i-cache-line-size = <64>;
> > +			i-cache-sets = <128>;
> > +			d-cache-size = <32768>;
> > +			d-cache-line-size = <64>;
> > +			d-cache-sets = <128>;
> > +			next-level-cache = <&l2_cache_l0>;
> > +			#cooling-cells = <2>;
> > +			dynamic-power-coefficient = <228>;
> > +		};
> 
> Is there any particular reason for not including more of the CPUs?

Yes, see below.

> > +		its: interrupt-controller@...40000 {
> > +			compatible = "arm,gic-v3-its";
> > +			msi-controller;
> > +			#msi-cells = <1>;
> > +			reg = <0x0 0xfe640000 0x0 0x20000>;
> > +		};
> > +	};
> 
> Does the ITS (and other bits related to GIC memory accesses) actually work,
> or will we have more of the same issues as RK356x?

The GIC in RK3588 is has the same shareability limitation as the RK356x,
but fixed the 32bit limitation. That's why I just added the boot cpu core
for now; adding any other cpu core breaks the boot without the downstream
shareability patch and I'm still investigating.

-- Sebastian

Download attachment "signature.asc" of type "application/pgp-signature" (834 bytes)