linux-kernel - [PATCH V2 0/2] Add complex scheduler level for arm64

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Message-ID: <SL2PR06MB30828131C046AB979BE75BD6BDFB9@SL2PR06MB3082.apcprd06.prod.outlook.com>
Date:   Tue, 26 Apr 2022 07:05:15 +0000
From:   王擎 <wangqing@...o.com>
To:     Sudeep Holla <sudeep.holla@....com>
CC:     Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "Rafael J. Wysocki" <rafael@...nel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "vincent.guittot@...aro.org" <vincent.guittot@...aro.org>,
        "dietmar.eggemann@....com" <dietmar.eggemann@....com>,
        Jonathan Cameron <Jonathan.Cameron@...wei.com>
Subject: [PATCH V2 0/2] Add complex scheduler level for arm64


Hi Sudeep:

I am thinking if it is possible to add a complex level cpu topology
between cluster and SMT?

We can describe it directly in “cpu-map”, instead of parsing it through
the cache info.

Thanks,
Qing

>>> From: Wang Qing <wangqing@...o.com>
>>> 
>>> The DSU cluster supports blocks that are called complexes
>>> which contain up to two cores of the same type and some shared logic,
>>> which sharing some logic between the cores can make a complex area efficient.
>>>
>>
>>Given the complex shares things like the SVE units (cortex a510)...
>>
>>Why not handle this as SMT?
>
>SMT should share all cache levels. but complexs only share L2(and L3)
>cache here.
>
>>
>>Seems like a blurred boundary between separate cores and SMT threads.
>>I think we need to express and potentially take advantage of knowledge
>>about what logic is being shared.
>
>Logic such as a Vector Processing Unit, L2 Translation Lookaside Buffer
>(TLB) ... are shared, I believe this will improve efficiency even if
>only L2 cache is shared.
>
>Thanks,
>Qing
>
>>
>>Jonathan
>>
>>> Complex also can be considered as a shared cache group smaller
>>> than cluster.
>>> 
>>> This patch adds complex level for complexs by parsing cache topology
>>> form DT. It will directly benefit a lot of workload which loves more
>>> resources such as memory bandwidth, caches.
>>> 
>>> Note this patch only handle the DT case.
>>> 
>>> V2:
>>> fix commit log and loop more
>>> 
>>> wangqing (2):
>>>   arch_topology: support for describing cache topology from DT
>>>   arm64: Add complex scheduler level for arm64
>>> 
>>>  arch/arm64/Kconfig            | 13 ++++++++++
>>>  arch/arm64/kernel/smp.c       | 48 ++++++++++++++++++++++++++++++++++-
>>>  drivers/base/arch_topology.c  | 47 +++++++++++++++++++++++++++++++++-
>>>  include/linux/arch_topology.h |  3 +++
>>>  4 files changed, 109 insertions(+), 2 deletions(-)
>>>