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Date: Wed, 27 Apr 2022 22:28:28 +0800
From: Jinlong Mao <quic_jinlmao@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@...ainline.org>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Suzuki K Poulose <suzuki.poulose@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>
CC: Mike Leach <mike.leach@...aro.org>, Leo Yan <leo.yan@...aro.org>,
"Greg Kroah-Hartman" <gregkh@...uxfoundation.org>,
<coresight@...ts.linaro.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
Tingwei Zhang <quic_tingweiz@...cinc.com>,
Yuanfang Zhang <quic_yuanfang@...cinc.com>,
Tao Zhang <quic_taozha@...cinc.com>,
Trilok Soni <quic_tsoni@...cinc.com>,
Hao Zhang <quic_hazha@...cinc.com>,
<linux-arm-msm@...r.kernel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>
Subject: Re: [PATCH v6 09/10] ARM: dts: msm: Add coresight components for
SM8250
Hi Konrad,
On 4/26/2022 7:53 PM, Konrad Dybcio wrote:
>
> On 25/04/2022 06:03, Mao Jinlong wrote:
>> Add coresight components for sm8250. STM/ETM are added.
>>
>> Signed-off-by: Tao Zhang <quic_taozha@...cinc.com>
>> Signed-off-by: Mao Jinlong <quic_jinlmao@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 488 +++++++++++++++++++++++++++
>> 1 file changed, 488 insertions(+)
>
> Hi,
>
> please fix the commit title to match the style used in the directory
> of the files you're changing.
I will update it.
>
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> index af8f22636436..53ab2b457a2f 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> @@ -4685,6 +4685,494 @@
>> interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1",
>> "dcvsh-irq-2";
>> #freq-domain-cells = <1>;
>> };
>
> If I can see correctly, you're putting these nodes right under
> cpufreq_hw, which has a unit address of 0x18591000, so this is not
> sorted properly.
>
>
I will update it.
> Konrad
>
>> +
>> + stm@...2000 {
>> + compatible = "arm,coresight-stm", "arm,primecell";
>> + reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>;
>> + reg-names = "stm-base", "stm-stimulus-base";
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + stm_out: endpoint {
>> + remote-endpoint = <&funnel0_in7>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@...1000 {
>> + compatible = "arm,coresight-dynamic-funnel",
>> "arm,primecell";
>> + reg = <0 0x06041000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + funnel0_out: endpoint {
>> + remote-endpoint = <&merge_funnel_in0>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@7 {
>> + reg = <7>;
>> + funnel0_in7: endpoint {
>> + remote-endpoint = <&stm_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@...2000 {
>> + compatible = "arm,coresight-dynamic-funnel",
>> "arm,primecell";
>> + reg = <0 0x06042000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + funnel2_out: endpoint {
>> + remote-endpoint = <&merge_funnel_in2>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@2 {
>> + reg = <4>;
>> + funnel2_in5: endpoint {
>> + remote-endpoint = <&apss_merge_funnel_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@...5000 {
>> + compatible = "arm,coresight-dynamic-funnel",
>> "arm,primecell";
>> + reg = <0 0x06045000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + funnel_merg_out_funnel_swao: endpoint {
>> + remote-endpoint =
>> <&funnel_swao_in_funnel_merg>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@1 {
>> + reg = <0>;
>> + merge_funnel_in0: endpoint {
>> + remote-endpoint = <&funnel0_out>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <1>;
>> + merge_funnel_in2: endpoint {
>> + remote-endpoint = <&funnel2_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + replicator@...6000 {
>> + compatible = "arm,coresight-dynamic-replicator",
>> "arm,primecell";
>> + reg = <0 0x06046000 0 0x1000>;
>> +
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + replicator_out: endpoint {
>> + remote-endpoint = <&etr_in>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + port {
>> + replicator_cx_in_swao_out: endpoint {
>> + remote-endpoint = <&replicator_swao_out_cx_in>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etr@...8000 {
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0 0x06048000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,scatter-gather;
>> +
>> + in-ports {
>> + port {
>> + etr_in: endpoint {
>> + remote-endpoint = <&replicator_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@...4000 {
>> + compatible = "arm,coresight-dynamic-funnel",
>> "arm,primecell";
>> + arm,primecell-periphid = <0x000bb908>;
>> +
>> + reg = <0 0x06b04000 0 0x1000>;
>> + reg-names = "funnel-base";
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + merge_funnel_out: endpoint {
>> + remote-endpoint = <&etf_in>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@7 {
>> + reg = <7>;
>> + funnel_swao_in_funnel_merg: endpoint {
>> + remote-endpoint=
>> <&funnel_merg_out_funnel_swao>;
>> + };
>> + };
>> + };
>> +
>> + };
>> +
>> + etf@...5000 {
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0 0x06b05000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + etf_out: endpoint {
>> + remote-endpoint = <&replicator_in>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@1 {
>> + reg = <0>;
>> + etf_in: endpoint {
>> + remote-endpoint = <&merge_funnel_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + replicator@...6000 {
>> + compatible = "arm,coresight-dynamic-replicator",
>> "arm,primecell";
>> + reg = <0 0x06b06000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + replicator_swao_out_cx_in: endpoint {
>> + remote-endpoint = <&replicator_cx_in_swao_out>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + port {
>> + replicator_in: endpoint {
>> + remote-endpoint = <&etf_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@...0000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07040000 0 0x1000>;
>> +
>> + cpu = <&CPU0>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm0_out: endpoint {
>> + remote-endpoint = <&apss_funnel_in0>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@...0000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07140000 0 0x1000>;
>> +
>> + cpu = <&CPU1>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm1_out: endpoint {
>> + remote-endpoint = <&apss_funnel_in1>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@...0000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07240000 0 0x1000>;
>> +
>> + cpu = <&CPU2>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm2_out: endpoint {
>> + remote-endpoint = <&apss_funnel_in2>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@...0000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07340000 0 0x1000>;
>> +
>> + cpu = <&CPU3>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm3_out: endpoint {
>> + remote-endpoint = <&apss_funnel_in3>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@...0000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07440000 0 0x1000>;
>> +
>> + cpu = <&CPU4>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm4_out: endpoint {
>> + remote-endpoint = <&apss_funnel_in4>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@...0000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07540000 0 0x1000>;
>> +
>> + cpu = <&CPU5>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm5_out: endpoint {
>> + remote-endpoint = <&apss_funnel_in5>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@...0000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07640000 0 0x1000>;
>> +
>> + cpu = <&CPU6>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm6_out: endpoint {
>> + remote-endpoint = <&apss_funnel_in6>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@...0000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07740000 0 0x1000>;
>> +
>> + cpu = <&CPU7>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm7_out: endpoint {
>> + remote-endpoint = <&apss_funnel_in7>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@...0000 {
>> + compatible = "arm,coresight-dynamic-funnel",
>> "arm,primecell";
>> + reg = <0 0x07800000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + apss_funnel_out: endpoint {
>> + remote-endpoint = <&apss_merge_funnel_in>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + apss_funnel_in0: endpoint {
>> + remote-endpoint = <&etm0_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + apss_funnel_in1: endpoint {
>> + remote-endpoint = <&etm1_out>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <2>;
>> + apss_funnel_in2: endpoint {
>> + remote-endpoint = <&etm2_out>;
>> + };
>> + };
>> +
>> + port@3 {
>> + reg = <3>;
>> + apss_funnel_in3: endpoint {
>> + remote-endpoint = <&etm3_out>;
>> + };
>> + };
>> +
>> + port@4 {
>> + reg = <4>;
>> + apss_funnel_in4: endpoint {
>> + remote-endpoint = <&etm4_out>;
>> + };
>> + };
>> +
>> + port@5 {
>> + reg = <5>;
>> + apss_funnel_in5: endpoint {
>> + remote-endpoint = <&etm5_out>;
>> + };
>> + };
>> +
>> + port@6 {
>> + reg = <6>;
>> + apss_funnel_in6: endpoint {
>> + remote-endpoint = <&etm6_out>;
>> + };
>> + };
>> +
>> + port@7 {
>> + reg = <7>;
>> + apss_funnel_in7: endpoint {
>> + remote-endpoint = <&etm7_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@...0000 {
>> + compatible = "arm,coresight-dynamic-funnel",
>> "arm,primecell";
>> + reg = <0 0x07810000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + apss_merge_funnel_out: endpoint {
>> + remote-endpoint = <&funnel2_in5>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + port@1 {
>> + reg = <0>;
>> + apss_merge_funnel_in: endpoint {
>> + remote-endpoint = <&apss_funnel_out>;
>> + };
>> + };
>> + };
>> + };
>> };
>> timer {
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