linux-kernel - [PATCH 2/5] dt-bindings: gpio: gpio-thunderx: Describe pin-cfg option

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20220427144620.9105-3-pmalgujar@marvell.com>
Date:   Wed, 27 Apr 2022 07:46:17 -0700
From:   Piyush Malgujar <pmalgujar@...vell.com>
To:     <linux-gpio@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <devicetree@...r.kernel.org>
CC:     <linus.walleij@...aro.org>, <brgl@...ev.pl>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <rric@...nel.org>,
        <cchavva@...vell.com>, <wsadowski@...vell.com>,
        Piyush Malgujar <pmalgujar@...vell.com>
Subject: [PATCH 2/5] dt-bindings: gpio: gpio-thunderx: Describe pin-cfg option

Add support for pin-cfg to configure GPIO Pins

Signed-off-by: Piyush Malgujar <pmalgujar@...vell.com>
---
 Documentation/devicetree/bindings/gpio/gpio-thunderx.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt
index 3f883ae29d116887e702ead20b26a25f9d2349d5..05f0be98afdcae941ff8a24c3fdabd8af83ccb87 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-thunderx.txt
@@ -14,6 +14,9 @@ Optional Properties:
                     "interrupt-controller" is present.
   - First cell is the GPIO pin number relative to the controller.
   - Second cell is triggering flags as defined in interrupts.txt.
+- pin-cfg: Configuration of pin's function, filters, XOR and output mode.
+  - First cell is the GPIO pin number
+  - Second cell is a value written to GPIO_BIT_CFG register at driver probe.
 
 Example:
 
@@ -24,4 +27,5 @@ gpio_6_0: gpio@6,0 {
 	#gpio-cells = <2>;
 	interrupt-controller;
 	#interrupt-cells = <2>;
+	pin-cfg = <57 0x2300000>, <58 0x2500000>;
 };
-- 
2.17.1