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Message-Id: <1651231749-19565-1-git-send-email-quic_c_spathi@quicinc.com>
Date:   Fri, 29 Apr 2022 16:59:09 +0530
From:   Srinivasarao Pathipati <quic_c_spathi@...cinc.com>
To:     will@...nel.org, mark.rutland@....com, peterz@...radead.org,
        mingo@...hat.com, acme@...nel.org,
        alexander.shishkin@...ux.intel.com, jolsa@...nel.org,
        namhyung@...nel.org, catalin.marinas@....com,
        linux-arm-kernel@...ts.infradead.org,
        linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org
Cc:     Srinivasarao Pathipati <quic_c_spathi@...cinc.com>
Subject: [PATCH V2] arm64: perf: Retain PMCR.X of PMCR_EL0 during reset

Preserve the bit PMCR.X of PMCR_EL0 during PMU reset to export
PMU events. as it could be set before PMU initialization.

Signed-off-by: Srinivasarao Pathipati <quic_c_spathi@...cinc.com>
---
Changes since V1:
	- Preserving only PMCR_X bit as per Robin Murphy's comment
---
 arch/arm64/kernel/perf_event.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index cb69ff1..532a417 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1047,6 +1047,9 @@ static void armv8pmu_reset(void *info)
 	if (armv8pmu_has_long_event(cpu_pmu))
 		pmcr |= ARMV8_PMU_PMCR_LP;
 
+	/* Preserve PMCR_X to export PMU events */
+	pmcr |= (armv8pmu_pmcr_read() & ARMV8_PMU_PMCR_X);
+
 	armv8pmu_pmcr_write(pmcr);
 }
 
-- 
2.7.4

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