linux-kernel - Re: [PATCH v7 5/5] perf arm-spe: Use SPE data source for neoverse cores

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Message-ID: <20220504162220.28528-1-alisaidi@amazon.com>
Date:   Wed, 4 May 2022 16:22:20 +0000
From:   Ali Saidi <alisaidi@...zon.com>
To:     <german.gomez@....com>
CC:     <Nick.Forrington@....com>, <acme@...nel.org>,
        <alexander.shishkin@...ux.intel.com>, <alisaidi@...zon.com>,
        <andrew.kilroy@....com>, <benh@...nel.crashing.org>,
        <james.clark@....com>, <john.garry@...wei.com>, <jolsa@...nel.org>,
        <kjain@...ux.ibm.com>, <leo.yan@...aro.org>,
        <lihuafei1@...wei.com>, <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <linux-perf-users@...r.kernel.org>,
        <mark.rutland@....com>, <mathieu.poirier@...aro.org>,
        <mingo@...hat.com>, <namhyung@...nel.org>, <peterz@...radead.org>,
        <will@...nel.org>
Subject: Re: [PATCH v7 5/5] perf arm-spe: Use SPE data source for neoverse cores

Hi German,

Thanks for taking another look!

On Tue, 3 May 2022 09:58:15 +0000, German Gomez wrote:
> Hi Ali, Leo
> 
> Some minor comments below.
> 
> On 26/04/2022 14:59, Ali Saidi wrote:
> > When synthesizing data from SPE, augment the type with source information
> > for Arm Neoverse cores. The field is IMPLDEF but the Neoverse cores all use
> > the same encoding. I can't find encoding information for any other SPE
> > implementations to unify their choices with Arm's thus that is left for
> > future work.
> >
> > This change populates the mem_lvl_num for Neoverse cores as well as the
> > deprecated mem_lvl namespace.
> >
> > Signed-off-by: Ali Saidi <alisaidi@...zon.com>
> > ---
> >  .../util/arm-spe-decoder/arm-spe-decoder.c    |   1 +
> >  .../util/arm-spe-decoder/arm-spe-decoder.h    |  12 ++
> >  tools/perf/util/arm-spe.c                     | 130 +++++++++++++++---
> >  3 files changed, 127 insertions(+), 16 deletions(-)
> >
> [snip]
> > +	/*
> > +	 * We have no data on the hit level or data source for stores in the
> > +	 * Neoverse SPE records.
> > +	 */
> > +	if (record->op & ARM_SPE_ST) {
> > +		data_src->mem_lvl = PERF_MEM_LVL_NA;
> > +		data_src->mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE;
> 
> Is it correct to use ANY_CACHE as the NA value? The LVLNUM_* enum begins at 1, so it looks like this should be set to 0 instead (like in HOPS_*).

I think you're making a good point here. To be consistent we should set
mem_lvl_num to PERF_MEM_LVLNUM_NA just like mem_lvl.

Thanks,
Ali