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Message-ID: <Ynk3vTtJApO13peb@sirena.org.uk>
Date: Mon, 9 May 2022 16:48:13 +0100
From: Mark Brown <broonie@...nel.org>
To: James Clark <james.clark@....com>
Cc: linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org, german.gomez@....com,
John Garry <john.garry@...wei.com>,
Will Deacon <will@...nel.org>,
Mathieu Poirier <mathieu.poirier@...aro.org>,
Leo Yan <leo.yan@...aro.org>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>,
Namhyung Kim <namhyung@...nel.org>, linux-doc@...r.kernel.org
Subject: Re: [PATCH v1 1/6] perf: arm64: Add SVE vector granule register to
user regs
On Mon, May 09, 2022 at 03:42:49PM +0100, James Clark wrote:
> Dwarf based unwinding in a function that pushes SVE registers onto
> the stack requires the unwinder to know the length of the SVE register
> to calculate the stack offsets correctly. This was added to the Arm
> specific Dwarf spec as the VG pseudo register[1].
>
> Add the vector length at position 46 if it's requested by userspace and
> SVE is supported. If it's not supported then fail to open the event.
>
> The vector length must be on each sample because it can be changed
> at runtime via a prctl or ptrace call. Also by adding it as a register
> rather than a separate attribute, minimal changes will be required in an
> unwinder that already indexes into the register list.
> +static u64 perf_ext_regs_value(int idx)
> +{
> + switch (idx) {
> + case PERF_REG_ARM64_VG:
> + if (WARN_ON_ONCE(!system_supports_sve()))
> + return 0;
These WARN_ON_ONCE()s seem a bit loud but I do see they are idiomatic
for this code so
Reviewed-by: Mark Brown <broonie@...nel.org>
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