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Message-ID: <34e48640-24a1-eaa2-e873-f7137aa47ba3@arm.com>
Date:   Tue, 10 May 2022 10:34:45 +0100
From:   James Clark <james.clark@....com>
To:     Mark Brown <broonie@...nel.org>
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-perf-users@...r.kernel.org, german.gomez@....com,
        John Garry <john.garry@...wei.com>,
        Will Deacon <will@...nel.org>,
        Mathieu Poirier <mathieu.poirier@...aro.org>,
        Leo Yan <leo.yan@...aro.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>, linux-doc@...r.kernel.org
Subject: Re: [PATCH v1 1/6] perf: arm64: Add SVE vector granule register to
 user regs



On 09/05/2022 16:48, Mark Brown wrote:
> On Mon, May 09, 2022 at 03:42:49PM +0100, James Clark wrote:
>> Dwarf based unwinding in a function that pushes SVE registers onto
>> the stack requires the unwinder to know the length of the SVE register
>> to calculate the stack offsets correctly. This was added to the Arm
>> specific Dwarf spec as the VG pseudo register[1].
>>
>> Add the vector length at position 46 if it's requested by userspace and
>> SVE is supported. If it's not supported then fail to open the event.
>>
>> The vector length must be on each sample because it can be changed
>> at runtime via a prctl or ptrace call. Also by adding it as a register
>> rather than a separate attribute, minimal changes will be required in an
>> unwinder that already indexes into the register list.
> 
>> +static u64 perf_ext_regs_value(int idx)
>> +{
>> +	switch (idx) {
>> +	case PERF_REG_ARM64_VG:
>> +		if (WARN_ON_ONCE(!system_supports_sve()))
>> +			return 0;
> 
> These WARN_ON_ONCE()s seem a bit loud but I do see they are idiomatic
> for this code so

They should never ever be hit because the mask is validated when opening
the event so hopefully it's not an issue.
 
> 
> Reviewed-by: Mark Brown <broonie@...nel.org>

Thanks Mark

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