lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <877d6t6xnb.wl-maz@kernel.org>
Date:   Tue, 10 May 2022 19:38:32 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     Antonio Borneo <antonio.borneo@...s.st.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Maxime Coquelin <mcoquelin.stm32@...il.com>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        <linux-kernel@...r.kernel.org>,
        <linux-stm32@...md-mailman.stormreply.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        Ludovic Barre <ludovic.barre@...s.st.com>,
        Loic Pallardy <loic.pallardy@...s.st.com>,
        Pascal Paillet <p.paillet@...s.st.com>
Subject: Re: [PATCH 3/7] irqchip/stm32-exti: remove EMR register access for stm32mp15

On Tue, 10 May 2022 17:41:19 +0100,
Antonio Borneo <antonio.borneo@...s.st.com> wrote:
> 
> From: Alexandre Torgue <alexandre.torgue@...s.st.com>
> 
> C1EMRx registers are not accessible on STM32MP15x.

And what happens if they are accessed? What are these registers for?

(notice a pattern here?)

	M.

> 
> Signed-off-by: Alexandre Torgue <alexandre.torgue@...s.st.com>
> Signed-off-by: Antonio Borneo <antonio.borneo@...s.st.com>
> ---
>  drivers/irqchip/irq-stm32-exti.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
> index 1145f064faa8..c8003f4f0457 100644
> --- a/drivers/irqchip/irq-stm32-exti.c
> +++ b/drivers/irqchip/irq-stm32-exti.c
> @@ -132,7 +132,6 @@ static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
>  
>  static const struct stm32_exti_bank stm32mp1_exti_b1 = {
>  	.imr_ofst	= 0x80,
> -	.emr_ofst	= 0x84,
>  	.rtsr_ofst	= 0x00,
>  	.ftsr_ofst	= 0x04,
>  	.swier_ofst	= 0x08,
> @@ -142,7 +141,6 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = {
>  
>  static const struct stm32_exti_bank stm32mp1_exti_b2 = {
>  	.imr_ofst	= 0x90,
> -	.emr_ofst	= 0x94,
>  	.rtsr_ofst	= 0x20,
>  	.ftsr_ofst	= 0x24,
>  	.swier_ofst	= 0x28,
> @@ -152,7 +150,6 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = {
>  
>  static const struct stm32_exti_bank stm32mp1_exti_b3 = {
>  	.imr_ofst	= 0xA0,
> -	.emr_ofst	= 0xA4,
>  	.rtsr_ofst	= 0x40,
>  	.ftsr_ofst	= 0x44,
>  	.swier_ofst	= 0x48,
> @@ -792,7 +789,8 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
>  	 * clear registers to avoid residue
>  	 */
>  	writel_relaxed(0, base + stm32_bank->imr_ofst);
> -	writel_relaxed(0, base + stm32_bank->emr_ofst);
> +	if (stm32_bank->emr_ofst)
> +		writel_relaxed(0, base + stm32_bank->emr_ofst);
>  
>  	pr_info("%pOF: bank%d\n", node, bank_idx);
>  
> -- 
> 2.36.0
> 
> 

-- 
Without deviation from the norm, progress is not possible.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ