linux-kernel - Re: [PATCH 0/2] perf: ARM CoreSight PMU support

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20220510184025.iwgknfqe5ygz4jwn@bogus>
Date:   Tue, 10 May 2022 19:40:25 +0100
From:   Sudeep Holla <sudeep.holla@....com>
To:     Besar Wicaksono <bwicaksono@...dia.com>
Cc:     Suzuki K Poulose <suzuki.poulose@....com>,
        Will Deacon <will@...nel.org>,
        Sudeep Holla <sudeep.holla@....com>, catalin.marinas@....com,
        mark.rutland@....com, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-tegra@...r.kernel.org,
        thanu.rangarajan@....com, Michael.Williams@....com,
        treding@...dia.com, jonathanh@...dia.com, vsethi@...dia.com,
        Mathieu Poirier <mathieu.poirier@...aro.org>
Subject: Re: [PATCH 0/2] perf: ARM CoreSight PMU support

On Tue, May 10, 2022 at 12:13:19PM +0100, Will Deacon wrote:
> On Tue, May 10, 2022 at 12:07:42PM +0100, Sudeep Holla wrote:
> > On Mon, May 09, 2022 at 11:02:23AM +0100, Suzuki K Poulose wrote:
> > > Cc: Mike Williams, Mathieu Poirier
> > > On 09/05/2022 10:28, Will Deacon wrote:
> > > > On Sun, May 08, 2022 at 07:28:08PM -0500, Besar Wicaksono wrote:
> > > > >   arch/arm64/configs/defconfig                  |    1 +
> > > > >   drivers/perf/Kconfig                          |    2 +
> > > > >   drivers/perf/Makefile                         |    1 +
> > > > >   drivers/perf/coresight_pmu/Kconfig            |   10 +
> > > > >   drivers/perf/coresight_pmu/Makefile           |    7 +
> > > > >   .../perf/coresight_pmu/arm_coresight_pmu.c    | 1317 +++++++++++++++++
> > > > >   .../perf/coresight_pmu/arm_coresight_pmu.h    |  147 ++
> > > > >   .../coresight_pmu/arm_coresight_pmu_nvidia.c  |  300 ++++
> > > > >   .../coresight_pmu/arm_coresight_pmu_nvidia.h  |   17 +
> > > > >   9 files changed, 1802 insertions(+)
> > > > 
> > > > How does this interact with all the stuff we have under
> > > > drivers/hwtracing/coresight/?
> > > 
> > > Absolutely zero, except for the name. The standard
> > > is named "CoreSight PMU" which is a bit unfortunate,
> > > given the only link, AFAIU, with the "CoreSight" architecture
> > > is the Lock Access Register(LAR). For reference, the
> > > drivers/hwtracing/coresight/ is purely "CoreSight" self-hosted
> > > tracing and the PMU is called "cs_etm" (expands to coresight etm).
> > > Otherwise the standard doesn't have anything to do with what
> > > exists already in the kernel.
>
> That's... a poor naming choice! But good, if it's entirely separate then I
> don't have to worry about that. Just wanted to make sure we're not going to
> get tangled up in things like ROM tables and Coresight power domains for
> these things.
>

OK, now that triggered another question/thought.

1. Do you need to do active power management for these PMUs ? Or like
   CPU PMUs, do you reject entering low power states if there is active
   session in progress. If there is active session, runtime PM won't get
   triggered but if there is system wide suspend, how is that dealt with ?

2. Assuming you need some sort of PM, and since this is static table(which
   I really don't like/prefer but it is out there 🙁), how do you plan to
   get the power domain related information.

-- 
Regards,
Sudeep