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Message-ID: <429ac287-04bd-af78-2deb-06426af53ea4@alliedtelesis.co.nz>
Date: Thu, 12 May 2022 00:54:52 +0000
From: Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To: Andrew Lunn <andrew@...n.ch>
CC: "robh+dt@...nel.org" <robh+dt@...nel.org>,
"krzysztof.kozlowski+dt@...aro.org"
<krzysztof.kozlowski+dt@...aro.org>,
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"will@...nel.org" <will@...nel.org>,
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"sebastian.hesselbarth@...il.com" <sebastian.hesselbarth@...il.com>,
"kostap@...vell.com" <kostap@...vell.com>,
"robert.marko@...tura.hr" <robert.marko@...tura.hr>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
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<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X
compatibles
On 12/05/22 12:45, Andrew Lunn wrote:
>> Yes there are registers that you can read to identify the specific chip.
>>
>> It still might be useful to have a expected vs actual check as those ID
>> values are determined by pin strapping resistors.
> That i don't get? Can i turn a
>
> * 98DX2538: 24x1G + 2x10G + 2x10G Stack
>
> into a
>
> * 98DX2535: 24x1G + 4x1G Stack
>
> by strapping its pin differently?
I'm not sure it'd actually work properly but yes there are external
PU/PD resistors that if you fitted differently would at least make the
ID say that a 98DX2538 is a 98DX2535. The HW docs have these as
"reserved" pins that must be pulled up/down depending on the specific part.
In reality I suspect that the different serdes arrangements are based on
what level of screening the silicon passed (similar to how some SoC
speed grades are distinguished). So you might be able to go down (i.e.
2538 -> 2535) but probably not up (i.e 2535 -> 2538).
>
>> It could also be used
>> to validate the dts (e.g. port 20 would be invalid on a 98DX3501). But
>> those are considerations for further down the track.
> Yes, that would be up to the switchdev driver to validate the DT based
> on the ID register.
>
> Andrew
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