linux-kernel - Re: [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X compatibles

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Message-ID: <6d1e121f-847b-3fc5-c27d-6504f380e4ef@alliedtelesis.co.nz>
Date:   Thu, 12 May 2022 01:20:50 +0000
From:   Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To:     Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "krzysztof.kozlowski+dt@...aro.org" 
        <krzysztof.kozlowski+dt@...aro.org>,
        "catalin.marinas@....com" <catalin.marinas@....com>,
        "will@...nel.org" <will@...nel.org>,
        "andrew@...n.ch" <andrew@...n.ch>,
        "gregory.clement@...tlin.com" <gregory.clement@...tlin.com>,
        "sebastian.hesselbarth@...il.com" <sebastian.hesselbarth@...il.com>,
        "kostap@...vell.com" <kostap@...vell.com>,
        "robert.marko@...tura.hr" <robert.marko@...tura.hr>
CC:     "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v6 1/3] dt-bindings: marvell: Document the AC5/AC5X
 compatibles


On 12/05/22 04:34, Krzysztof Kozlowski wrote:
> On 11/05/2022 01:10, Chris Packham wrote:
>> Describe the compatible properties for the Marvell Alleycat5/5X switches
>> with integrated CPUs.
>>
>> Alleycat5:
>> * 98DX2538: 24x1G + 2x10G + 2x10G Stack
>> * 98DX2535: 24x1G + 4x1G Stack
>> * 98DX2532: 8x1G + 2x10G + 2x1G Stack
>> * 98DX2531: 8x1G + 4x1G Stack
>> * 98DX2528: 24x1G + 2x10G + 2x10G Stack
>> * 98DX2525: 24x1G + 4x1G Stack
>> * 98DX2522: 8x1G + 2x10G + 2x1G Stack
>> * 98DX2521: 8x1G + 4x1G Stack
>> * 98DX2518: 24x1G + 2x10G + 2x10G Stack
>> * 98DX2515: 24x1G + 4x1G Stack
>> * 98DX2512: 8x1G + 2x10G + 2x1G Stack
>> * 98DX2511: 8x1G + 4x1G Stack
>>
>> Alleycat5X:
>> * 98DX3500: 24x1G + 6x25G
>> * 98DX3501: 16x1G + 6x10G
>> * 98DX3510: 48x1G + 6x25G
>> * 98DX3520: 24x2.5G + 6x25G
>> * 98DX3530: 48x2.5G + 6x25G
>> * 98DX3540: 12x5G/6x10G + 6x25G
>> * 98DX3550: 24x5G/12x10G + 6x25G
>>
>> Signed-off-by: Chris Packham <chris.packham@...iedtelesis.co.nz>
>> ---
>>
>> Notes:
>>      Changes in v6:
>>      - New
>>
>>   .../bindings/arm/marvell/armada-98dx2530.yaml | 27 +++++++++++++++++++
>>   1 file changed, 27 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/arm/marvell/armada-98dx2530.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-98dx2530.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-98dx2530.yaml
>> new file mode 100644
>> index 000000000000..6d9185baf0c5
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/marvell/armada-98dx2530.yaml
>> @@ -0,0 +1,27 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://scanmail.trustwave.com/?c=20988&d=heX74s-dh8HSCAJmafRigZHOoyY0XQDl80QSCXWitw&u=http%3a%2f%2fdevicetree%2eorg%2fschemas%2farm%2fmarvell%2farmada-98dx2530%2eyaml%23
>> +$schema: http://scanmail.trustwave.com/?c=20988&d=heX74s-dh8HSCAJmafRigZHOoyY0XQDl80oVWnOltA&u=http%3a%2f%2fdevicetree%2eorg%2fmeta-schemas%2fcore%2eyaml%23
>> +
>> +title: Marvell Alleycat5/5X Platforms
>> +
>> +maintainers:
>> +  - Chris Packham <chris.packham@...iedtelesis.co.nz>
>> +
>> +properties:
>> +  $nodename:
>> +    const: '/'
>> +  compatible:
>> +    oneOf:
>> +
>> +      - description: Alleycat5 (98DX25xx)
>> +        items:
>> +          - const: marvell,ac5
> This is confusing and does not look correct. The DTS calls AC5 a SoC and
> you cannot have SoC alone. It's unusable without a SoM or board.
>
>> +
>> +      - description: Alleycat5X (98DX35xx)
>> +        items:
>> +          - const: marvell,ac5x
>> +          - const: marvell,ac5
> This entry looks correct except ac5x once is called a SoC and once a
> RD-AC5X board.
>
> It cannot be both. Probably you need third compatible, assuming AC5x is
> a flavor of AC5.

Yeah it's a bit confusing

RD-AC5X-(bunch of extra numbers and letters) is the board I have.
AC5X is a L3 switch chip with integrated CPU.
AC5 is a L3 switch chip with integrated CPU.

Switch wise the AC5X and AC5 are quite different but the CPU block is 
the same between the two.

>
> items:
>   - enum:
>       - marvell,rd-ac5x
>   - const: marvell,ac5x
>   - const: marvell,ac5

I can go with that but I'm a little vague on what the requirements are. 
I was trying to follow the armada-7k-8k.yaml as an example.

If I look at the cn9130-crb-A board it ends up with:

   compatible = "marvell,cn9130", "marvell,armada-ap807-quad", 
"marvell,armada-ap807";

I know the ap807 has something to do with the vagaries of the cn9130 SoC 
but isn't the "marvell,cn9130" still referring to the SoC. From what 
you've said shouldn't there be a "marvell,cn9130-crb" somewhere in the mix?

Perhaps I've picked a bad example but the other dtbs I've poked at don't 
have any board binding.

>> +
>> +additionalProperties: true
>
> Best regards,
> Krzysztof