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Message-ID: <CAMuHMdUiq3svPa+OMmG70HP-3h4gKV6puoT8QUm3WgPw+e4i=A@mail.gmail.com>
Date: Thu, 12 May 2022 09:29:34 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Cc: Linus Walleij <linus.walleij@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>,
Philipp Zabel <p.zabel@...gutronix.de>,
"open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
Phil Edworthy <phil.edworthy@...esas.com>,
Biju Das <biju.das.jz@...renesas.com>,
Prabhakar <prabhakar.csengg@...il.com>
Subject: Re: [PATCH v3 4/5] gpio: gpiolib: Add ngirq member to struct gpio_irq_chip
Hi Prabhakar,
On Wed, May 11, 2022 at 8:32 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> Supported GPIO IRQs by the chip is not always equal to the number of GPIO
> pins. For example on Renesas RZ/G2L SoC where it has GPIO0-122 pins but at
> a give point a maximum of only 32 GPIO pins can be used as IRQ lines in
> the IRQC domain.
>
> This patch adds ngirq member to struct gpio_irq_chip and passes this as a
> size to irq_domain_create_hierarchy()/irq_domain_create_simple() if it is
> being set in the driver otherwise fallbacks to using ngpio.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Thanks for your patch!
> --- a/drivers/gpio/gpiolib.c
> +++ b/drivers/gpio/gpiolib.c
> @@ -1221,7 +1221,7 @@ static int gpiochip_hierarchy_add_domain(struct gpio_chip *gc)
> gc->irq.domain = irq_domain_create_hierarchy(
> gc->irq.parent_domain,
> 0,
> - gc->ngpio,
> + gc->irq.ngirq ?: gc->ngpio,
> gc->irq.fwnode,
> &gc->irq.child_irq_domain_ops,
> gc);
> @@ -1574,7 +1574,7 @@ static int gpiochip_add_irqchip(struct gpio_chip *gc,
> } else {
> /* Some drivers provide custom irqdomain ops */
> gc->irq.domain = irq_domain_create_simple(fwnode,
> - gc->ngpio,
> + gc->irq.ngirq ?: gc->ngpio,
> gc->irq.first,
> gc->irq.domain_ops ?: &gpiochip_domain_ops,
> gc);
OK.
gpiochip_irqchip_remove() does:
/* Remove all IRQ mappings and delete the domain */
if (gc->irq.domain) {
unsigned int irq;
for (offset = 0; offset < gc->ngpio; offset++) {
if (!gpiochip_irqchip_irq_valid(gc, offset))
Hence it relies on gc->irq.valid_mask, which I think is OK in general.
continue;
irq = irq_find_mapping(gc->irq.domain, offset);
irq_dispose_mapping(irq);
}
irq_domain_remove(gc->irq.domain);
}
> --- a/include/linux/gpio/driver.h
> +++ b/include/linux/gpio/driver.h
> @@ -51,6 +51,14 @@ struct gpio_irq_chip {
> */
> const struct irq_domain_ops *domain_ops;
>
> + /**
> + * @ngirq:
> + *
> + * The number of GPIO IRQ's handled by this IRQ domain; usually is
> + * equal to ngpio.
"If not set, ngpio will be used."
> + */
> + u16 ngirq;
> +
> #ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
> /**
> * @fwnode:
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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