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Message-ID: <20220516091934.263141-2-hugues.fruchet@foss.st.com>
Date:   Mon, 16 May 2022 11:19:32 +0200
From:   Hugues Fruchet <hugues.fruchet@...s.st.com>
To:     Mauro Carvalho Chehab <mchehab@...nel.org>,
        Sakari Ailus <sakari.ailus@...ux.intel.com>,
        Benjamin Mugnier <benjamin.mugnier@...s.st.com>,
        Sylvain Petinot <sylvain.petinot@...s.st.com>
CC:     <linux-media@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Alain Volmat <alain.volmat@...s.st.com>,
        Hugues Fruchet <hugues.fruchet@...s.st.com>
Subject: [PATCH 1/3] media: st-mipid02: add support of pixel clock polarity

Add support of pixel clock polarity.

Signed-off-by: Hugues Fruchet <hugues.fruchet@...s.st.com>
---
 drivers/media/i2c/st-mipid02.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/media/i2c/st-mipid02.c b/drivers/media/i2c/st-mipid02.c
index ef976d085d72..59b48026c752 100644
--- a/drivers/media/i2c/st-mipid02.c
+++ b/drivers/media/i2c/st-mipid02.c
@@ -50,6 +50,7 @@
 /* Bits definition for MIPID02_MODE_REG2 */
 #define MODE_HSYNC_ACTIVE_HIGH				BIT(1)
 #define MODE_VSYNC_ACTIVE_HIGH				BIT(2)
+#define MODE_PCLK_SAMPLE_RISING				BIT(3)
 /* Bits definition for MIPID02_DATA_SELECTION_CTRL */
 #define SELECTION_MANUAL_DATA				BIT(2)
 #define SELECTION_MANUAL_WIDTH				BIT(3)
@@ -494,6 +495,8 @@ static int mipid02_configure_from_tx(struct mipid02_dev *bridge)
 		bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH;
 	if (ep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
 		bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH;
+	if (ep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
+		bridge->r.mode_reg2 |= MODE_PCLK_SAMPLE_RISING;
 
 	return 0;
 }
-- 
2.25.1

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