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Message-ID: <20220516091934.263141-1-hugues.fruchet@foss.st.com>
Date: Mon, 16 May 2022 11:19:31 +0200
From: Hugues Fruchet <hugues.fruchet@...s.st.com>
To: Mauro Carvalho Chehab <mchehab@...nel.org>,
Sakari Ailus <sakari.ailus@...ux.intel.com>,
Benjamin Mugnier <benjamin.mugnier@...s.st.com>,
Sylvain Petinot <sylvain.petinot@...s.st.com>
CC: <linux-media@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Alain Volmat <alain.volmat@...s.st.com>,
Hugues Fruchet <hugues.fruchet@...s.st.com>
Subject: [PATCH 0/3] MIPID02 pixel clk polarity & serial pixel formats
Enhance MIPID02 CSI-2 to parallel bridge with pixel clock polarity
support and support of 1X16 CSI-2 serial pixel formats.
Alain Volmat (1):
media: st-mipid02: add support for YVYU and VYUY formats
Hugues Fruchet (2):
media: st-mipid02: add support of pixel clock polarity
media: st-mipid02: expose 1X16 serial pixel format
drivers/media/i2c/st-mipid02.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
--
2.25.1
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