lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Tue, 17 May 2022 11:40:46 -0400 From: Yang Weijiang <weijiang.yang@...el.com> To: pbonzini@...hat.com, jmattson@...gle.com, seanjc@...gle.com, like.xu.linux@...il.com, vkuznets@...hat.com, kan.liang@...ux.intel.com, wei.w.wang@...el.com, kvm@...r.kernel.org, linux-kernel@...r.kernel.org Cc: Like Xu <like.xu@...ux.intel.com>, Peter Zijlstra <peterz@...radead.org>, Andi Kleen <ak@...ux.intel.com>, Yang Weijiang <weijiang.yang@...el.com> Subject: [PATCH v12 02/16] perf/x86/lbr: Simplify the exposure check for the LBR_INFO registers From: Like Xu <like.xu@...ux.intel.com> The x86_pmu.lbr_info is 0 unless explicitly initialized, so there's no point checking x86_pmu.intel_cap.lbr_format. Cc: Peter Zijlstra <peterz@...radead.org> Reviewed-by: Kan Liang <kan.liang@...ux.intel.com> Reviewed-by: Andi Kleen <ak@...ux.intel.com> Signed-off-by: Like Xu <like.xu@...ux.intel.com> Signed-off-by: Yang Weijiang <weijiang.yang@...el.com> --- arch/x86/events/intel/lbr.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index fe1742c4ca49..4529ce448b2e 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -1874,12 +1874,10 @@ void __init intel_pmu_arch_lbr_init(void) */ int x86_perf_get_lbr(struct x86_pmu_lbr *lbr) { - int lbr_fmt = x86_pmu.intel_cap.lbr_format; - lbr->nr = x86_pmu.lbr_nr; lbr->from = x86_pmu.lbr_from; lbr->to = x86_pmu.lbr_to; - lbr->info = (lbr_fmt == LBR_FORMAT_INFO) ? x86_pmu.lbr_info : 0; + lbr->info = x86_pmu.lbr_info; return 0; } -- 2.27.0
Powered by blists - more mailing lists