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Message-Id: <1652866528-13220-2-git-send-email-hongxing.zhu@nxp.com>
Date: Wed, 18 May 2022 17:35:28 +0800
From: Richard Zhu <hongxing.zhu@....com>
To: l.stach@...gutronix.de, bhelgaas@...gle.com,
lorenzo.pieralisi@....com, festevam@...il.com
Cc: hongxing.zhu@....com, linux-pci@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
kernel@...gutronix.de, linux-imx@....com
Subject: [RFC 2/2] PCI: imx6: Support more than Gen2 speed link mode
Support more than Gen2 speed link mode, since i.MX8MP PCIe supports up
to Gen3 link speed.
Signed-off-by: Richard Zhu <hongxing.zhu@....com>
---
drivers/pci/controller/dwc/pci-imx6.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 30641d2dda14..37012f9a33a0 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -809,8 +809,8 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
dw_pcie_wait_for_link(pci);
- if (pci->link_gen == 2) {
- /* Allow Gen2 mode after the link is up. */
+ if (pci->link_gen > 1) {
+ /* Allow faster modes after the link is up. */
dw_pcie_dbi_ro_wr_en(pci);
tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
tmp &= ~PCI_EXP_LNKCAP_SLS;
--
2.25.1
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