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Message-ID: <20220711221701.GA697090@bhelgaas>
Date: Mon, 11 Jul 2022 17:17:01 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Richard Zhu <hongxing.zhu@....com>
Cc: l.stach@...gutronix.de, bhelgaas@...gle.com,
lorenzo.pieralisi@....com, festevam@...il.com,
linux-pci@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, kernel@...gutronix.de,
linux-imx@....com
Subject: Re: [RFC 1/2] PCI: imx6: Make sure the DBI register can be changed
Hi Richard,
On Wed, May 18, 2022 at 05:35:27PM +0800, Richard Zhu wrote:
> The PCIE_DBI_RO_WR_EN bit should be set when write some DBI registers.
> To make sure that the DBI registers are writable, set the
> PCIE_DBI_RO_WR_EN properly when touch the DBI registers.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 6619e3caffe2..30641d2dda14 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -797,10 +797,12 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
> * started in Gen2 mode, there is a possibility the devices on the
> * bus will not be detected at all. This happens with PCIe switches.
> */
> + dw_pcie_dbi_ro_wr_en(pci);
What's the status of this patch? I don't see this change included in
your v14 series [1]. That series has a lot of imx6 updates, so I
would have thought you'd include this change in it. Or maybe this
change turned out not to be needed?
What about the 2/2 patch?
They're both marked "RFC" which is sometimes a hint that the author
isn't really committed to the patch, so sometimes they don't get the
attention they deserve.
Bjorn
[1] https://lore.kernel.org/r/1656645935-1370-1-git-send-email-hongxing.zhu@nxp.com
> tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> tmp &= ~PCI_EXP_LNKCAP_SLS;
> tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
> dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
> + dw_pcie_dbi_ro_wr_dis(pci);
>
> /* Start LTSSM. */
> imx6_pcie_ltssm_enable(dev);
> @@ -809,6 +811,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
>
> if (pci->link_gen == 2) {
> /* Allow Gen2 mode after the link is up. */
> + dw_pcie_dbi_ro_wr_en(pci);
> tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
> tmp &= ~PCI_EXP_LNKCAP_SLS;
> tmp |= PCI_EXP_LNKCAP_SLS_5_0GB;
> @@ -821,6 +824,7 @@ static int imx6_pcie_start_link(struct dw_pcie *pci)
> tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
> tmp |= PORT_LOGIC_SPEED_CHANGE;
> dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
> + dw_pcie_dbi_ro_wr_dis(pci);
>
> if (imx6_pcie->drvdata->flags &
> IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
> --
> 2.25.1
>
>
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