linux-kernel - Re: [RFC PATCH 1/4] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CA+V-a8sxZOZRXG_gsCnQGJdNDw-uVLmuTZ-dOsmUfhS9KL0Esg@mail.gmail.com>
Date:   Thu, 19 May 2022 06:44:45 +0100
From:   "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Biju Das <biju.das.jz@...renesas.com>,
        Phil Edworthy <phil.edworthy@...esas.com>
Subject: Re: [RFC PATCH 1/4] dt-bindings: clock: r9a07g043-cpg: Add Renesas
 RZ/Five CPG Clock and Reset Definitions

Hi Geert,

Thank you for the review.

On Tue, May 10, 2022 at 3:02 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Thu, May 5, 2022 at 9:32 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> > Renesas RZ/Five SoC has almost the same clock structure compared to the
> > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just
> > ammend the RZ/Five CPG clock and reset definitions.
>
> amend
>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> > --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> > +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> > @@ -108,6 +108,15 @@
> >  #define R9A07G043_ADC_ADCLK            76
> >  #define R9A07G043_ADC_PCLK             77
> >  #define R9A07G043_TSU_PCLK             78
> > +#define R9A07G043_NCEPLDM_DM_CLK       79      /* RZ/Five Only */
>
> While NCEPLDM_DM_CLK is listed in the clock list spreadsheet, its
> control bit is not documented.
>
> > +#define R9A07G043_NCEPLDM_ACLK         80      /* RZ/Five Only */
> > +#define R9A07G043_NCEPLDM_TCK          81      /* RZ/Five Only */
>
> While NCEPLDM_TCK is listed in the clock list spreadsheet, its
> control bit is not documented.
>
I have got the feedback for the above, NCEPLDM_DM_CLK and NCEPLDM_TCK
clocks cannot be stopped as a result there are no register bits for it
in the HW manual (clock spreadsheet will be updated). I will drop this
and send a v2 including your RB.

Cheers,
Prabhakar

> The rest LGTM, so with the above clarified
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds