linux-kernel - Re: [RFC PATCH 1/4] dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions

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Message-ID: <CAMuHMdW0hbVnCcbcC5E8J7Jc_UZPVSpHkmtPd3Haio-WnhhbpQ@mail.gmail.com>
Date:   Thu, 19 May 2022 08:57:04 +0200
From:   Geert Uytterhoeven <geert@...ux-m68k.org>
To:     "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-clk <linux-clk@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Biju Das <biju.das.jz@...renesas.com>,
        Phil Edworthy <phil.edworthy@...esas.com>
Subject: Re: [RFC PATCH 1/4] dt-bindings: clock: r9a07g043-cpg: Add Renesas
 RZ/Five CPG Clock and Reset Definitions

Hi Prabhakar,

On Thu, May 19, 2022 at 7:45 AM Lad, Prabhakar
<prabhakar.csengg@...il.com> wrote:
> On Tue, May 10, 2022 at 3:02 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> > On Thu, May 5, 2022 at 9:32 PM Lad Prabhakar
> > <prabhakar.mahadev-lad.rj@...renesas.com> wrote:
> > > Renesas RZ/Five SoC has almost the same clock structure compared to the
> > > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just
> > > ammend the RZ/Five CPG clock and reset definitions.
> >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > > --- a/include/dt-bindings/clock/r9a07g043-cpg.h
> > > +++ b/include/dt-bindings/clock/r9a07g043-cpg.h
> > > @@ -108,6 +108,15 @@
> > >  #define R9A07G043_ADC_ADCLK            76
> > >  #define R9A07G043_ADC_PCLK             77
> > >  #define R9A07G043_TSU_PCLK             78
> > > +#define R9A07G043_NCEPLDM_DM_CLK       79      /* RZ/Five Only */
> >
> > While NCEPLDM_DM_CLK is listed in the clock list spreadsheet, its
> > control bit is not documented.
> >
> > > +#define R9A07G043_NCEPLDM_ACLK         80      /* RZ/Five Only */
> > > +#define R9A07G043_NCEPLDM_TCK          81      /* RZ/Five Only */
> >
> > While NCEPLDM_TCK is listed in the clock list spreadsheet, its
> > control bit is not documented.
> >
> I have got the feedback for the above, NCEPLDM_DM_CLK and NCEPLDM_TCK
> clocks cannot be stopped as a result there are no register bits for it
> in the HW manual (clock spreadsheet will be updated). I will drop this
> and send a v2 including your RB.

The question is not if the clocks can be stopped or not, but if there
is any need to refer to them from a DT node.
What's the nature of the future update to the clock spreadsheet?

Of course, if we don't add these clock definitions now, they can
still be added later. DT binding definitions are append-only.

Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds