linux-kernel - [PATCH v2 2/3] fpga: region: Add fpga-region 'power-domains' property

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Message-ID: <20220523134517.4056873-3-nava.manne@xilinx.com>
Date:   Mon, 23 May 2022 19:15:16 +0530
From:   Nava kishore Manne <nava.manne@...inx.com>
To:     <mdf@...nel.org>, <hao.wu@...el.com>, <yilun.xu@...el.com>,
        <trix@...hat.com>, <robh+dt@...nel.org>,
        <krzysztof.kozlowski+dt@...aro.org>, <michal.simek@...inx.com>,
        <nava.manne@...inx.com>, <linux-fpga@...r.kernel.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, <git@...inx.com>
CC:     Rob Herring <robh@...nel.org>
Subject: [PATCH v2 2/3] fpga: region: Add fpga-region 'power-domains' property

Add fpga-region 'power-domains' property to allow to handle
the FPGA/PL power domains.

Signed-off-by: Nava kishore Manne <nava.manne@...inx.com>
Acked-by: Rob Herring <robh@...nel.org>
---
Changes for v2:
              - Updated power-domains description.

 .../devicetree/bindings/fpga/fpga-region.txt       | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/fpga/fpga-region.txt b/Documentation/devicetree/bindings/fpga/fpga-region.txt
index 7d3515264838..f299c3749505 100644
--- a/Documentation/devicetree/bindings/fpga/fpga-region.txt
+++ b/Documentation/devicetree/bindings/fpga/fpga-region.txt
@@ -196,6 +196,20 @@ Optional properties:
 - config-complete-timeout-us : The maximum time in microseconds time for the
 	FPGA to go to operating mode after the region has been programmed.
 - child nodes : devices in the FPGA after programming.
+- power-domains : A phandle and power domain specifier pair to the power domain
+	which is responsible for turning on/off the power to the FPGA/PL region.
+Example:
+	fpga_full: fpga-full {
+                compatible = "fpga-region";
+                fpga-mgr = <&zynqmp_pcap>;
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                power-domains = <&zynqmp_firmware PL_PD>;
+        };
+
+	The PL_PD power domain will be turned on before loading the bitstream
+and turned off while removing/unloading the bitstream using overlays.
 
 In the example below, when an overlay is applied targeting fpga-region0,
 fpga_mgr is used to program the FPGA.  Two bridges are controlled during
-- 
2.25.1