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Message-ID: <03f0e3b5-8007-2731-62be-6e9fd18b949b@linaro.org>
Date: Mon, 23 May 2022 16:16:46 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Geert Uytterhoeven <geert@...ux-m68k.org>
Cc: Tomer Maimon <tmaimon77@...il.com>,
Avi Fishman <avifishman70@...il.com>,
Tali Perry <tali.perry1@...il.com>,
Joel Stanley <joel@....id.au>,
Patrick Venture <venture@...gle.com>,
Nancy Yuen <yuenn@...gle.com>,
Benjamin Fair <benjaminfair@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
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"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
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Subject: Re: [PATCH v1 17/19] arm64: dts: nuvoton: Add initial NPCM8XX device
tree
On 23/05/2022 15:58, Geert Uytterhoeven wrote:
> Hi Krzysztof,
>
> On Mon, May 23, 2022 at 11:08 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@...aro.org> wrote:
>> On 22/05/2022 17:50, Tomer Maimon wrote:
>>> This adds initial device tree support for the
>>> Nuvoton NPCM845 Board Management controller (BMC) SoC family.
>>
>> Thank you for your patch. There is something to discuss/improve.
>>
>>> The NPCM845 based quad-core Cortex-A35 ARMv8 architecture and
>>> have various peripheral IPs.
>>>
>>> Signed-off-by: Tomer Maimon <tmaimon77@...il.com>
>
>>> + l2: l2-cache {
>>> + compatible = "cache";
>>
>> Is this a real compatible? What bindings are you using here?
>
> The compatible value and related properties are defined in the
> Devicetree Specification, v0.4-rc1, Section 3.9 ("Multi-level and
> Shared Cache Nodes (/cpus/cpu*/l?-cache)").
Indeed, thanks!
>
> The properties are handled by
> dtschema/schemas/cache-controller.yaml, but the latter seems to lack
> any checking on the compatible value?
Best regards,
Krzysztof
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