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Message-ID: <CAHp75Vc3i6bWOo_ZHD25rtn0o1pjzHtdfRQg4RkAfrmMs77eOw@mail.gmail.com>
Date: Mon, 30 May 2022 14:24:00 +0200
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Arnd Bergmann <arnd@...db.de>
Cc: Tomer Maimon <tmaimon77@...il.com>,
Avi Fishman <avifishman70@...il.com>,
Tali Perry <tali.perry1@...il.com>,
Joel Stanley <joel@....id.au>,
Patrick Venture <venture@...gle.com>,
Nancy Yuen <yuenn@...gle.com>,
Benjamin Fair <benjaminfair@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
gregkh <gregkh@...uxfoundation.org>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Wim Van Sebroeck <wim@...ux-watchdog.org>,
Guenter Roeck <linux@...ck-us.net>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>, Olof Johansson <olof@...om.net>,
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Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>,
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Subject: Re: [PATCH v1 00/19] Introduce Nuvoton Arbel NPCM8XX BMC SoC
On Mon, May 23, 2022 at 1:59 PM Arnd Bergmann <arnd@...db.de> wrote:
>
> On Sun, May 22, 2022 at 5:50 PM Tomer Maimon <tmaimon77@...il.com> wrote:
> >
> > This patchset adds initial support for the Nuvoton
> > Arbel NPCM8XX Board Management controller (BMC) SoC family.
> >
> > The Nuvoton Arbel NPCM8XX SoC is a fourth-generation BMC.
> > The NPCM8XX computing subsystem comprises a quadcore ARM
> > Cortex A35 ARM-V8 architecture.
> >
> > This patchset adds minimal architecture and drivers such as:
> > Clocksource, Clock, Reset, and WD.
> >
> > Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
> >
> > This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Thanks for your submission. Please note a few things about the process here:
>
> - The merge window is currently open, which means a lo
Something wrong with the script?
> Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
>
> This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Tomer Maimon (19):
> dt-bindings: timer: npcm: Add npcm845 compatible string
> clocksource: timer-npcm7xx: Add NPCM845 timer support
> dt-bindings: serial: 8250: Add npcm845 compatible string
> tty: serial: 8250: Add NPCM845 UART support
> dt-bindings: watchdog: npcm: Add npcm845 compatible string
> watchdog: npcm_wdt: Add NPCM845 watchdog support
> dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
> clk: npcm8xx: add clock controller
> dt-bindings: reset: add syscon property
> reset: npcm: using syscon instead of device data
> dt-bindings: reset: npcm: Add support for NPCM8XX
> reset: npcm: Add NPCM8XX support
> dt-bindings: arm: npcm: Add maintainer
> dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
> dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
> arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
> arm64: dts: nuvoton: Add initial NPCM8XX device tree
> arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
> arm64: defconfig: Add Nuvoton NPCM family supportt of maintainers
> won't be reviewing your patches at the moment. It may be better to wait
> for the -rc1 to be out before sending out v2
>
> - don't send your patches to soc@...nel.org unless you want me to pick
> them up into the soc tree and they have been reviewed already. The series
> is clearly still under review at the moment, and I expect it to go through
> a few revisions first.
>
> - gmail marked your emails as possible spam for me. I don't know what
> happened here, but you may want to look into this to ensure that
> everybody receives it.
>
> Some of the Arbel NPCM8XX peripherals are based on Poleg NPCM7XX.
>
> This patchset was tested on the Arbel NPCM8XX evaluation board.
>
> Tomer Maimon (19):
> dt-bindings: timer: npcm: Add npcm845 compatible string
> clocksource: timer-npcm7xx: Add NPCM845 timer support
> dt-bindings: serial: 8250: Add npcm845 compatible string
> tty: serial: 8250: Add NPCM845 UART support
> dt-bindings: watchdog: npcm: Add npcm845 compatible string
> watchdog: npcm_wdt: Add NPCM845 watchdog support
> dt-binding: clk: npcm845: Add binding for Nuvoton NPCM8XX Clock
> clk: npcm8xx: add clock controller
> dt-bindings: reset: add syscon property
> reset: npcm: using syscon instead of device data
> dt-bindings: reset: npcm: Add support for NPCM8XX
> reset: npcm: Add NPCM8XX support
> dt-bindings: arm: npcm: Add maintainer
> dt-bindings: arm: npcm: Add nuvoton,npcm845 compatible string
> dt-bindings: arm: npcm: Add nuvoton,npcm845 GCR compatible string
> arm64: npcm: Add support for Nuvoton NPCM8XX BMC SoC
> arm64: dts: nuvoton: Add initial NPCM8XX device tree
> arm64: dts: nuvoton: Add initial NPCM845 EVB device tree
> arm64: defconfig: Add Nuvoton NPCM family support
>
> - For an initial platform submission, I can merge the
> clk/clocksource/serial/reset drivers along with the platform if they
> have an Ack from the subsystem maintainers. I would normally
> not include the watchdog patch in this as it's not essential, but
> I suppose that it's fine if you only do a oneline change and it
> has an Ack. If you have other nonessential drivers that need changes,
> best submit them separately though.
>
> Arnd
--
With Best Regards,
Andy Shevchenko
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