linux-kernel - Re: [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size

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Message-ID: <4376261.8F6SAcFxjW@diego>
Date:   Wed, 25 May 2022 17:14:31 +0200
From:   Heiko Stübner <heiko@...ech.de>
To:     Rob Herring <robh@...nel.org>
Cc:     palmer@...belt.com, paul.walmsley@...ive.com,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
        wefu@...hat.com, guoren@...nel.org, atishp@...shpatra.org,
        anup@...infault.org, mick@....forth.gr, samuel@...lland.org,
        cmuellner@...ux.com, philipp.tomsich@...ll.eu, krzk+dt@...nel.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: document cbom-block-size

Am Mittwoch, 18. Mai 2022, 02:25:29 CEST schrieb Rob Herring:
> On Wed, May 11, 2022 at 11:41:30PM +0200, Heiko Stuebner wrote:
> > The Zicbom operates on a block-size defined for the cpu-core,
> > which does not necessarily match other cache-sizes used.
> > 
> > So add the necessary property for the system to know the core's
> > block-size.
> > 
> > Signed-off-by: Heiko Stuebner <heiko@...ech.de>
> > ---
> >  Documentation/devicetree/bindings/riscv/cpus.yaml | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index d632ac76532e..b179bfd155a3 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -63,6 +63,13 @@ properties:
> >        - riscv,sv48
> >        - riscv,none
> >  
> > +  riscv,cbom-block-size:
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> 
> Any value 0-2^32 is valid?

funnily enough there really seems to be _no_ constraints defined in the
spec [0] regarding the actual cache-block size.

It essentially only states
"The capacity and organization of a cache and the size of a
cache block are both implementation-specific"

and later in software-discovery:
"The initial set of CMO extensions requires the following information to
be discovered by software:
- The size of the cache block for management and prefetch instructions
- The size of the cache block for zero instructions"



[0] https://github.com/riscv/riscv-CMOs/blob/master/specifications/cmobase-v1.0.pdf


> 
> > +    description:
> > +      Blocksize in bytes for the Zicbom cache operations. The block
> > +      size is a property of the core itself and does not necessarily
> > +      match other software defined cache sizes.
> 
> What about hardware defined cache sizes? I'm scratching my head as to 
> what a 'software defined cache size' is.
> 
> > +
> >    riscv,isa:
> >      description:
> >        Identifies the specific RISC-V instruction set architecture
>