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Message-Id: <20220526101131.2340729-1-sunilvl@ventanamicro.com>
Date: Thu, 26 May 2022 15:41:26 +0530
From: Sunil V L <sunilvl@...tanamicro.com>
To: Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Ard Biesheuvel <ardb@...nel.org>,
Marc Zyngier <maz@...nel.org>,
Atish Patra <atishp@...osinc.com>,
Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
Anup Patel <apatel@...tanamicro.com>
Cc: linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-efi@...r.kernel.org, Sunil V L <sunil.vl@...il.com>,
Sunil V L <sunilvl@...tanamicro.com>
Subject: [PATCH V2 0/5] Support for 64bit hartid on RV64 platforms
The hartid can be a 64bit value on RV64 platforms. This series updates
the code so that 64bit hartid can be supported on RV64 platforms.
The series has been tested on both RV32 and RV64 qemu platforms.
Changes since V1:
1) Updated RB tag for PATCH 1 and PATCH3
2) Type Casting NR_CPUS before comparing with hartid in PATCH 2
3) Changed commit message of PATCH 2 to provide details about
the bug it is fixing.
4) Updated PATCH 5 for unaligned 64bit read
Sunil V L (5):
riscv: cpu_ops_sbi: Support for 64bit hartid
riscv: spinwait: Fix hartid variable type
riscv: smp: Support for 64bit hartid
riscv: cpu: Support for 64bit hartid
riscv/efi_stub: Support for 64bit boot-hartid
arch/riscv/include/asm/processor.h | 4 ++--
arch/riscv/include/asm/smp.h | 4 ++--
arch/riscv/kernel/cpu.c | 26 +++++++++++++----------
arch/riscv/kernel/cpu_ops_sbi.c | 4 ++--
arch/riscv/kernel/cpu_ops_spinwait.c | 4 ++--
arch/riscv/kernel/cpufeature.c | 6 ++++--
arch/riscv/kernel/smp.c | 4 ++--
arch/riscv/kernel/smpboot.c | 9 ++++----
drivers/clocksource/timer-riscv.c | 15 +++++++------
drivers/firmware/efi/libstub/riscv-stub.c | 13 +++++++++---
drivers/irqchip/irq-riscv-intc.c | 7 +++---
drivers/irqchip/irq-sifive-plic.c | 7 +++---
12 files changed, 60 insertions(+), 43 deletions(-)
--
2.25.1
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