lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <trinity-b1d8205a-3354-42e7-8784-0a0cfd7e8a36-1654177662388@3c-app-gmx-bs39>
Date:   Thu, 2 Jun 2022 15:47:42 +0200
From:   Frank Wunderlich <frank-w@...lic-files.de>
To:     Rob Herring <robh@...nel.org>
Cc:     Frank Wunderlich <linux@...web.de>,
        Michael Riesch <michael.riesch@...fvision.net>,
        Vinod Koul <vkoul@...nel.org>,
        Johan Jonker <jbx6244@...il.com>,
        linux-rockchip@...ts.infradead.org, linux-pci@...r.kernel.org,
        Kishon Vijay Abraham I <kishon@...com>,
        linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Peter Geis <pgwipeout@...il.com>,
        Heiko Stuebner <heiko@...ech.de>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        Krzysztof WilczyƄski <kw@...ux.com>
Subject: Aw: Re: Re: [RFC v3 1/5] dt-bindings: phy: rockchip: add PCIe v3
 phy

> Gesendet: Freitag, 20. Mai 2022 um 13:50 Uhr
> Von: "Frank Wunderlich" <frank-w@...lic-files.de>
> An: "Rob Herring" <robh@...nel.org>
> Hi,
>
> fixed reg-error by using 32bit-address in example, in my test output is clean.
>
> +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> @@ -68,7 +68,7 @@ examples:
>      #include <dt-bindings/clock/rk3568-cru.h>
>      pcie30phy: phy@...c0000 {
>        compatible = "rockchip,rk3568-pcie3-phy";
> -      reg = <0x0 0xfe8c0000 0x0 0x20000>;
> +      reg = <0xfe8c0000 0x20000>;
>
>
> i hope yours is clean too

have you tried it?

> regarding data-lanes instead of own lane-map, Peter and me only find this in special
> bindings outside the phy-"namespace" like this.
>
> https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/media/video-interfaces.yaml#L157
>
> do you mean converting this binding and add it there and base out binding on it?
>
> https://elixir.bootlin.com/linux/v5.18-rc7/source/Documentation/devicetree/bindings/phy/phy-bindings.txt

is this the right binding to add the data-lanes or do you refer another one (have not found phy-provider)?

regards Frank

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ