[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <2955958b-4982-42bc-7c68-82cd23462b35@huawei.com>
Date: Mon, 13 Jun 2022 11:09:01 +0100
From: John Garry <john.garry@...wei.com>
To: Nick Forrington <nick.forrington@....com>,
<linux-kernel@...r.kernel.org>, <linux-perf-users@...r.kernel.org>,
<acme@...nel.org>
CC: Will Deacon <will@...nel.org>, James Clark <james.clark@....com>,
"Mike Leach" <mike.leach@...aro.org>, Leo Yan <leo.yan@...aro.org>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Mark Rutland <mark.rutland@....com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Jiri Olsa <jolsa@...nel.org>,
"Namhyung Kim" <namhyung@...nel.org>,
Andrew Kilroy <andrew.kilroy@....com>,
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH] perf vendor events arm64: Arm Cortex-A78C and X1C
On 10/06/2022 18:44, Nick Forrington wrote:
> Add PMU events for the Arm Cortex-A78C and Arm Cortex-X1C CPUs.
>
> Events for Arm Cortex-A78C match those for Arm Cortex-A78.
> Events for Arm Cortex-X1C match those for Arm Cortex- X1.
>
> As such, this is just a mapfile change.
>
> Main ID Register (MIDR) and event data is sourced from the corresponding
> Arm Technical Reference Manuals:
>
> Arm Cortex-A78C
> https://developer.arm.com/documentation/102226/
>
> Arm Cortex-X1C
> https://developer.arm.com/documentation/101968/
>
> Signed-off-by: Nick Forrington<nick.forrington@....com>
Reviewed-by: John Garry <john.garry@...wei.com>
Powered by blists - more mailing lists