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Message-ID: <20220614161118.12458-1-quic_tdas@quicinc.com>
Date: Tue, 14 Jun 2022 21:41:18 +0530
From: Taniya Das <quic_tdas@...cinc.com>
To: Rob Herring <robh+dt@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>
CC: Douglas Anderson <dianders@...omium.org>,
Stephen Boyd <swboyd@...omium.org>,
Andy Gross <agross@...nel.org>, <devicetree@...r.kernel.org>,
<linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Taniya Das <quic_tdas@...cinc.com>
Subject: [PATCH v1] arm64: dts: qcom: sc7280: Update lpassaudio clock controller for resets
The lpass audio supports TX/RX/WSA block resets. The LPASS PIL clock
driver is not supported and mark it disabled. Also to keep consistency
update lpasscore to lpass_core.
Fixes: 9499240d15f2 ("arm64: dts: qcom: sc7280: Add lpasscore & lpassaudio clock controllers")
Signed-off-by: Taniya Das <quic_tdas@...cinc.com>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index e66fc67de206..180cfd2765b9 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2174,6 +2174,7 @@
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
#clock-cells = <1>;
+ status = "disabled";
};
lpass_audiocc: clock-controller@...0000 {
@@ -2185,6 +2186,7 @@
power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
+ #reset-cells = <1>;
};
lpass_aon: clock-controller@...0000 {
@@ -2198,7 +2200,7 @@
#power-domain-cells = <1>;
};
- lpasscore: clock-controller@...0000 {
+ lpass_core: clock-controller@...0000 {
compatible = "qcom,sc7280-lpasscorecc";
reg = <0 0x03900000 0 0x50000>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
--
2.17.1
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