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Message-ID: <4670aab9-b7fa-f2c7-567a-12ca24535b0c@alliedtelesis.co.nz>
Date: Tue, 14 Jun 2022 05:11:01 +0000
From: Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To: Vadym Kochan <vadym.kochan@...ision.eu>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Catalin Marinas <catalin.marinas@....com>,
Will Deacon <will@...nel.org>,
Gregory CLEMENT <gregory.clement@...tlin.com>,
Konstantin Porotchkin <kostap@...vell.com>,
Robert Marko <robert.marko@...tura.hr>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v9 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and
RD-AC5X board
On 14/06/22 10:53, Vadym Kochan wrote:
> From: Chris Packham <chris.packham@...iedtelesis.co.nz>
>
> The 98DX2530 SoC is the Control and Management CPU integrated into
> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally
> referred to as AlleyCat5 and AlleyCat5X).
>
> These files have been taken from the Marvell SDK and lightly cleaned
> up with the License and copyright retained.
>
> Signed-off-by: Chris Packham <chris.packham@...iedtelesis.co.nz>
> Signed-off-by: Vadym Kochan <vadym.kochan@...ision.eu>
> ---
>
> Notes:
> The Marvell SDK has a number of new compatible strings. I've brought
> through some of the drivers or where possible used an in-tree
> alternative (e.g. there is SDK code for a ac5-gpio but two instances of
> the existing marvell,orion-gpio seems to cover what is needed if you use
> an appropriate binding). I expect that there will a new series of
> patches when I get some different hardware (or additions to this series
> depending on if/when it lands).
>
> Changes in v9 (proposed by Marvell):
> It was discussed with Chris that Marvell will add some changes:
>
> 1) Rename "armada-" prefix in dts(i) file names to ac5, because
> Armada has not much common with AC5 SoC.
>
> 2) Add clock fixes:
> - rename core_clock to cnm_clock
> - remove axi_clock
> - change cnm_clock to 325MHZ
> - use cnm_clock for the UART
>
> Changes in v8:
> - Remove unnecessary clock-frequency property on armv8-timer
> - Remove unnecessary redistributor-stride property on gic
> - Add GIC_SPI interrupts for gpios
> Changes in v7:
> - Add missing compatible on usb1
> - Add "rd-ac5x" compatible for board
> - Move aliases to board dts
> - Move board specific usb info to board dts
> - Consolidate usb1 board settings and remove unnecessary compatible
> - Add Allied Telesis copyright
> - Rename files after mailng-list discussion
> Changes in v6:
> - Move CPU nodes above the SoC (Krzysztof)
> - Minor formatting clean ups (Krzysztof)
> - Run through `make dtbs_check`
> - Move gic nodes inside SoC
> - Group clocks under a clock node
> Changes in v5:
> - add #{address,size}-cells property to i2c nodes
> - make i2c nodes disabled in the SoC and enable them in the board
> - add interrupt controller attributes to gpio nodes
> - Move fixed-clock nodes up a level and remove unnecessary @0
> Changes in v4:
> - use 'phy-handle' instead of 'phy'
> - move status="okay" on usb nodes to board dts
> - Add review from Andrew
> Changes in v3:
> - Move memory node to board
> - Use single digit reg value for phy address
> - Remove MMC node (driver needs work)
> - Remove syscon & simple-mfd for pinctrl
> Changes in v2:
> - Make pinctrl a child node of a syscon node
> - Use marvell,armada-8k-gpio instead of orion-gpio
> - Remove nand peripheral. The Marvell SDK does have some changes for the
> ac5-nand-controller but I currently lack hardware with NAND fitted so
> I can't test it right now. I've therefore chosen to omit the node and
> not attempted to bring in the driver or binding.
> - Remove pcie peripheral. Again there are changes in the SDK and I have
> no way of testing them.
> - Remove prestera node.
> - Remove "marvell,ac5-ehci" compatible from USB node as
> "marvell,orion-ehci" is sufficient
> - Remove watchdog node. There is a buggy driver for the ac5 watchdog in
> the SDK but it needs some work so I've dropped the node for now.
>
> arch/arm64/boot/dts/marvell/Makefile | 1 +
> arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi | 291 ++++++++++++++++++
> .../boot/dts/marvell/ac5-98dx35xx-rd.dts | 101 ++++++
> arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi | 13 +
> 4 files changed, 406 insertions(+)
> create mode 100644 arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> create mode 100644 arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts
> create mode 100644 arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi
>
> diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
> index 1c794cdcb8e6..b6d493e34dc5 100644
> --- a/arch/arm64/boot/dts/marvell/Makefile
> +++ b/arch/arm64/boot/dts/marvell/Makefile
> @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb
> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb
> +dtb-$(CONFIG_ARCH_MVEBU) += ac5-98dx35xx-rd.dtb
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> new file mode 100644
> index 000000000000..cf0b4a7de323
> --- /dev/null
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx25xx.dtsi
> @@ -0,0 +1,291 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree For AC5.
> + *
> + * Copyright (C) 2021 Marvell
> + * Copyright (C) 2022 Allied Telesis Labs
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + model = "Marvell AC5 SoC";
> + compatible = "marvell,ac5";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&cpu0>;
> + };
> + core1 {
> + cpu = <&cpu1>;
> + };
> + };
> + };
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,armv8";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
Marvell confirmed to me that the EL2 virtual timer is not connected to
an interrupt.
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + dma-ranges;
> +
> + internal-regs@...00000 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + /* 16M internal register @ 0x7f00_0000 */
> + ranges = <0x0 0x0 0x7f000000 0x1000000>;
> + dma-coherent;
> +
> + uart0: serial@...00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x12000 0x100>;
> + reg-shift = <2>;
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + reg-io-width = <1>;
> + clocks = <&cnm_clock>;
With this change I see some garbled output when the "Serial: AMBA PL011
UART" driver starts.
It could be that my bootloader has the same wrong clock value as the
earlier iteration of this device tree.
> + status = "okay";
> + };
> +
> + mdio: mdio@...04 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "marvell,orion-mdio";
> + reg = <0x22004 0x4>;
> + clocks = <&cnm_clock>;
> + };
> +
> + i2c0: i2c@...00{
> + compatible = "marvell,mv78230-i2c";
> + reg = <0x11000 0x20>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + clocks = <&cnm_clock>;
> + clock-names = "core";
> + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency=<100000>;
> +
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-1 = <&i2c0_gpio>;
> + scl_gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
> + sda_gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@...00{
> + compatible = "marvell,mv78230-i2c";
> + reg = <0x11100 0x20>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + clocks = <&cnm_clock>;
> + clock-names = "core";
> + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency=<100000>;
> +
> + pinctrl-names = "default", "gpio";
> + pinctrl-0 = <&i2c1_pins>;
> + pinctrl-1 = <&i2c1_gpio>;
> + scl_gpio = <&gpio0 20 GPIO_ACTIVE_HIGH>;
> + sda_gpio = <&gpio0 21 GPIO_ACTIVE_HIGH>;
> + status = "disabled";
> + };
> +
> + gpio0: gpio@...00 {
> + compatible = "marvell,orion-gpio";
> + reg = <0x18100 0x40>;
> + ngpios = <32>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl0 0 0 32>;
> + marvell,pwm-offset = <0x1f0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + gpio1: gpio@...40 {
> + reg = <0x18140 0x40>;
> + compatible = "marvell,orion-gpio";
> + ngpios = <14>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&pinctrl0 0 32 14>;
> + marvell,pwm-offset = <0x1f0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + /*
> + * Dedicated section for devices behind 32bit controllers so we
> + * can configure specific DMA mapping for them
> + */
> + behind-32bit-controller@...00000 {
> + compatible = "simple-bus";
> + #address-cells = <0x2>;
> + #size-cells = <0x2>;
> + ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>;
> + /* Host phy ram starts at 0x200M */
> + dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>;
> + dma-coherent;
> +
> + eth0: ethernet@...00 {
> + compatible = "marvell,armada-ac5-neta";
> + reg = <0x0 0x20000 0x0 0x4000>;
> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cnm_clock>;
> + phy-mode = "sgmii";
> + status = "disabled";
> + };
> +
> + eth1: ethernet@...00 {
> + compatible = "marvell,armada-ac5-neta";
> + reg = <0x0 0x24000 0x0 0x4000>;
> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cnm_clock>;
> + phy-mode = "sgmii";
> + status = "disabled";
> + };
> +
> + usb0: usb@...00 {
> + compatible = "marvell,orion-ehci";
> + reg = <0x0 0x80000 0x0 0x500>;
> + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + usb1: usb@...00 {
> + compatible = "marvell,orion-ehci";
> + reg = <0x0 0xa0000 0x0 0x500>;
> + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> + };
> +
> + pinctrl0: pinctrl@...20100 {
> + compatible = "marvell,ac5-pinctrl";
> + reg = <0 0x80020100 0 0x20>;
> +
> + i2c0_pins: i2c0-pins {
> + marvell,pins = "mpp26", "mpp27";
> + marvell,function = "i2c0";
> + };
> +
> + i2c0_gpio: i2c0-gpio-pins {
> + marvell,pins = "mpp26", "mpp27";
> + marvell,function = "gpio";
> + };
> +
> + i2c1_pins: i2c1-pins {
> + marvell,pins = "mpp20", "mpp21";
> + marvell,function = "i2c1";
> + };
> +
> + i2c1_gpio: i2c1-gpio-pins {
> + marvell,pins = "mpp20", "mpp21";
> + marvell,function = "i2c1";
> + };
> + };
> +
> + spi0: spi@...a0000 {
> + compatible = "marvell,armada-3700-spi";
> + reg = <0x0 0x805a0000 0x0 0x50>;
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + clocks = <&spi_clock>;
> + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + spi1: spi@...a8000 {
> + compatible = "marvell,armada-3700-spi";
> + reg = <0x0 0x805a8000 0x0 0x50>;
> + #address-cells = <0x1>;
> + #size-cells = <0x0>;
> + clocks = <&spi_clock>;
> + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + gic: interrupt-controller@...00000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */
> + <0x0 0x80660000 0x0 0x40000>; /* GICR */
> + interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + clocks {
> + cnm_clock: core-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <325000000>;
> + };
> +
> + spi_clock: spi-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts b/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts
> new file mode 100644
> index 000000000000..f0ebdb84eec9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx35xx-rd.dts
> @@ -0,0 +1,101 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree For RD-AC5X.
> + *
> + * Copyright (C) 2021 Marvell
> + * Copyright (C) 2022 Allied Telesis Labs
> + */
> +/*
> + * Device Tree file for Marvell Alleycat 5X development board
> + * This board file supports the B configuration of the board
> + */
> +
> +/dts-v1/;
> +
> +#include "ac5-98dx35xx.dtsi"
> +
> +/ {
> + model = "Marvell RD-AC5X Board";
> + compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
> +
> + aliases {
> + serial0 = &uart0;
> + spiflash0 = &spiflash0;
> + gpio0 = &gpio0;
> + gpio1 = &gpio1;
> + ethernet0 = ð0;
> + ethernet1 = ð1;
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x2 0x00000000 0x0 0x40000000>;
> + };
> +
> + usb1phy: usb-phy {
> + compatible = "usb-nop-xceiv";
> + #phy-cells = <0>;
> + };
> +};
> +
> +&mdio {
> + phy0: ethernet-phy@0 {
> + reg = <0>;
> + };
> +};
> +
> +&i2c0 {
> + status = "okay";
> +};
> +
> +&i2c1 {
> + status = "okay";
> +};
> +
> +ð0 {
> + status = "okay";
> + phy-handle = <&phy0>;
> +};
> +
> +/* USB0 is a host USB */
> +&usb0 {
> + status = "okay";
> +};
> +
> +/* USB1 is a peripheral USB */
> +&usb1 {
> + status = "okay";
> + phys = <&usb1phy>;
> + phy-names = "usb-phy";
> + dr_mode = "peripheral";
> +};
> +
> +&spi0 {
> + status = "okay";
> +
> + spiflash0: flash@0 {
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> + spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> + reg = <0>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "spi_flash_part0";
> + reg = <0x0 0x800000>;
> + };
> +
> + parition@1 {
> + label = "spi_flash_part1";
> + reg = <0x800000 0x700000>;
> + };
> +
> + parition@2 {
> + label = "spi_flash_part2";
> + reg = <0xF00000 0x100000>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi b/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi
> new file mode 100644
> index 000000000000..50d464d9d2f4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/marvell/ac5-98dx35xx.dtsi
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree For AC5X.
> + *
> + * Copyright (C) 2022 Allied Telesis Labs
> + */
> +
> +#include "ac5-98dx25xx.dtsi"
> +
> +/ {
> + model = "Marvell AC5X SoC";
> + compatible = "marvell,ac5x", "marvell,ac5";
> +};
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