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Message-ID: <20220615163146.GA1397011-robh@kernel.org>
Date: Wed, 15 Jun 2022 10:31:46 -0600
From: Rob Herring <robh@...nel.org>
To: Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc: devicetree@...r.kernel.org,
Pavel Parkhomenko <Pavel.Parkhomenko@...kalelectronics.ru>,
linux-kernel@...r.kernel.org,
Serge Semin <fancer.lancer@...il.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Frank Li <Frank.Li@....com>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof WilczyĆski <kw@...ux.com>,
Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
Jingoo Han <jingoohan1@...il.com>, linux-pci@...r.kernel.org
Subject: Re: [PATCH v3 06/17] dt-bindings: PCI: dwc: Add max-functions EP
property
On Fri, 10 Jun 2022 11:56:54 +0300, Serge Semin wrote:
> In accordance with [1] the CX_NFUNC IP-core synthesize parameter is
> responsible for the number of physical functions to support in the EP
> mode. Its upper limit is 32. Let's use it to constrain the number of
> PCIe functions the DW PCIe EP DT-nodes can advertise.
>
> [1] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe
> Endpoint, Version 5.40a, March 2019, p. 887.
>
> Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru>
>
> ---
>
> Changelog v3:
> - This is a new patch unpinned from the next one:
> https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@baikalelectronics.ru/
> by the Rob' request. (@Rob)
> ---
> Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Reviewed-by: Rob Herring <robh@...nel.org>
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