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Message-ID: <20220615145550.GA1069883-robh@kernel.org>
Date: Wed, 15 Jun 2022 08:55:50 -0600
From: Rob Herring <robh@...nel.org>
To: Serge Semin <Sergey.Semin@...kalelectronics.ru>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
Jingoo Han <jingoohan1@...il.com>,
Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Serge Semin <fancer.lancer@...il.com>,
Alexey Malahov <Alexey.Malahov@...kalelectronics.ru>,
Pavel Parkhomenko <Pavel.Parkhomenko@...kalelectronics.ru>,
Krzysztof WilczyĆski <kw@...ux.com>,
Frank Li <Frank.Li@....com>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 04/17] dt-bindings: PCI: dwc: Add max-link-speed
common property
On Fri, Jun 10, 2022 at 11:56:52AM +0300, Serge Semin wrote:
> In accordance with [1] DW PCIe controllers support up to Gen5 link speed.
> Let's add the max-link-speed property upper bound to 5 then. The DT
> bindings of the particular devices are expected to setup more strict
> constraint on that parameter.
>
> [1] Synopsys DesignWare Cores PCI Express Controller Databook, Version
> 5.40a, March 2019, p. 27
>
> Signed-off-by: Serge Semin <Sergey.Semin@...kalelectronics.ru>
>
> ---
>
> Changelog v3:
> - This is a new patch unpinned from the next one:
> https://lore.kernel.org/linux-pci/20220503214638.1895-2-Sergey.Semin@baikalelectronics.ru/
> by the Rob' request. (@Rob)
> ---
> Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml | 3 +++
> Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 ++
> Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> index 627a5d6625ba..b2fbe886981b 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> @@ -45,6 +45,9 @@ properties:
> the peripheral devices available on the PCIe bus.
> maxItems: 1
>
> + max-link-speed:
> + maximum: 5
Unless the default is less than the max, shouldn't the max here be 1
less than the h/w max?
> +
> num-lanes:
> description:
> Number of PCIe link lanes to use. Can be omitted should the already
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
> index dcd521aed213..fc3b5d4ac245 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml
> @@ -55,4 +55,6 @@ examples:
>
> phys = <&pcie_phy0>, <&pcie_phy1>, <&pcie_phy2>, <&pcie_phy3>;
> phy-names = "pcie0", "pcie1", "pcie2", "pcie3";
> +
> + max-link-speed = <3>;
> };
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> index 4a5c8b933b52..01cedf51e0f8 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
> @@ -74,4 +74,5 @@ examples:
> phy-names = "pcie";
>
> num-lanes = <1>;
> + max-link-speed = <3>;
This should give you an error because pci-bus.yaml only goes up to 4.
I'm not really sure that limiting it in the common schema is too useful.
We're going to be updating it one step at a time. Limiting it is really
only helpful for specific implementations.
Patch 1 didn't apply for me, so none of the checks ran.
Rob
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