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Message-Id: <20220616015128.5697EC341C0@smtp.kernel.org>
Date: Wed, 15 Jun 2022 18:51:25 -0700
From: Stephen Boyd <sboyd@...nel.org>
To: Rex-BC Chen <rex-bc.chen@...iatek.com>,
krzysztof.kozlowski+dt@...aro.org, matthias.bgg@...il.com,
mturquette@...libre.com, robh+dt@...nel.org
Cc: p.zabel@...gutronix.de, angelogioacchino.delregno@...labora.com,
nfraprado@...labora.com, chun-jie.chen@...iatek.com,
wenst@...omium.org, runyang.chen@...iatek.com,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
Project_Global_Chrome_Upstream_Group@...iatek.com,
Rex-BC Chen <rex-bc.chen@...iatek.com>
Subject: Re: [RESEND v8 05/19] clk: mediatek: reset: Merge and revise reset register function
Quoting Rex-BC Chen (2022-05-23 02:33:32)
> There are two versions for clock reset register control for MediaTek
> SoCs. The old hardware is one bit per reset control, and does not
> have separate registers for bit set, clear and read-back operations.
> This matches the scheme supported by the simple reset driver.
>
> However, because we need to use different data structure from
> reset_simple_data, we can not use the operation of simple reset
> driver.
> For this reason, we keep the original functions and name this version
> as "MTK_RST_SIMPLE".
>
> In this patch:
> - Add a version enumeration to separate different reset hardware.
> - Merge the reset register function of simple and set_clr into one
> function "mtk_register_reset_controller".
> - Rename input variable "num_regs" to "rst_bank_nr" to avoid
> confusion. This variable is used to define the quantity of reset bank.
> - Document mtk_reset_version and mtk_register_reset_controller.
>
> Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> Reviewed-by: NĂcolas F. R. A. Prado <nfraprado@...labora.com>
> Tested-by: NĂcolas F. R. A. Prado <nfraprado@...labora.com>
> ---
Applied to clk-next
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