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Date: Thu, 16 Jun 2022 17:06:27 +0530 From: Ravi Bangoria <ravi.bangoria@....com> To: <peterz@...radead.org>, <acme@...nel.org> CC: <ravi.bangoria@....com>, <jolsa@...nel.org>, <namhyung@...nel.org>, <eranian@...gle.com>, <irogers@...gle.com>, <jmario@...hat.com>, <leo.yan@...aro.org>, <alisaidi@...zon.com>, <ak@...ux.intel.com>, <kan.liang@...ux.intel.com>, <dave.hansen@...ux.intel.com>, <hpa@...or.com>, <mingo@...hat.com>, <mark.rutland@....com>, <alexander.shishkin@...ux.intel.com>, <tglx@...utronix.de>, <bp@...en8.de>, <x86@...nel.org>, <linux-perf-users@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <sandipan.das@....com>, <ananth.narayan@....com>, <kim.phillips@....com>, <santosh.shukla@....com> Subject: [PATCH v2 04/14] perf/x86/amd: Support PERF_SAMPLE_{WEIGHT|WEIGHT_STRUCT} IbsDcMissLat indicates the number of clock cycles from when a miss is detected in the data cache to when the data was delivered to the core. Similarly, IbsTagToRetCtr provides number of cycles from when the op was tagged to when the op was retired. Consider these fields for sample->weight. Note that sample->weight will be populated only when PERF_SAMPLE_DATA_SRC is also set, although PERF_SAMPLE_WEIGHT_STRUCT and PERF_SAMPLE_WEIGHT are independent of PERF_SAMPLE_DATA_SRC. Signed-off-by: Ravi Bangoria <ravi.bangoria@....com> --- arch/x86/events/amd/ibs.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index de2632a2e44d..830e527a29c3 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -714,6 +714,7 @@ static u8 perf_ibs_data_src(union ibs_op_data2 *op_data2) } static void perf_ibs_get_mem_lvl(struct perf_event *event, + union ibs_op_data *op_data, union ibs_op_data2 *op_data2, union ibs_op_data3 *op_data3, struct perf_sample_data *data) @@ -738,6 +739,16 @@ static void perf_ibs_get_mem_lvl(struct perf_event *event, return; } + /* Load latency (Data cache miss latency) */ + if (data_src->mem_op == PERF_MEM_OP_LOAD) { + if (event->attr.sample_type & PERF_SAMPLE_WEIGHT_STRUCT) { + data->weight.var1_dw = op_data3->dc_miss_lat; + data->weight.var2_w = op_data->tag_to_ret_ctr; + } else if (event->attr.sample_type & PERF_SAMPLE_WEIGHT) { + data->weight.full = op_data3->dc_miss_lat; + } + } + /* L2 Hit */ if (op_data3->l2_miss == 0) { /* Erratum #1293 */ @@ -935,6 +946,7 @@ static void perf_ibs_get_data_src(struct perf_event *event, struct perf_sample_data *data) { union perf_mem_data_src *data_src = &data->data_src; + union ibs_op_data op_data; union ibs_op_data2 op_data2; union ibs_op_data3 op_data3; @@ -945,6 +957,7 @@ static void perf_ibs_get_data_src(struct perf_event *event, data_src->mem_op != PERF_MEM_OP_STORE) return; + op_data.val = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSOPDATA)]; op_data2.val = ibs_data->regs[ibs_op_msr_idx(MSR_AMD64_IBSOPDATA2)]; /* Erratum #1293 */ @@ -958,7 +971,7 @@ static void perf_ibs_get_data_src(struct perf_event *event, op_data2.val = 0; } - perf_ibs_get_mem_lvl(event, &op_data2, &op_data3, data); + perf_ibs_get_mem_lvl(event, &op_data, &op_data2, &op_data3, data); perf_ibs_get_mem_snoop(&op_data2, data); perf_ibs_get_tlb_lvl(&op_data3, data); perf_ibs_get_mem_lock(&op_data3, data); -- 2.31.1
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