linux-kernel - Re: [PATCH V6 0/2] riscv: Support qspinlock with generic headers

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Message-ID: <7adc9e19-7ffc-4b11-3e18-6e3a5225638f@redhat.com>
Date:   Tue, 21 Jun 2022 11:08:21 -0400
From:   Waiman Long <longman@...hat.com>
To:     guoren@...nel.org, palmer@...osinc.com, arnd@...db.de,
        peterz@...radead.org, boqun.feng@...il.com,
        Conor.Dooley@...rochip.com, chenhuacai@...ngson.cn,
        kernel@...0n.name, r@....cc, shorne@...il.com
Cc:     linux-riscv@...ts.infradead.org, linux-arch@...r.kernel.org,
        linux-kernel@...r.kernel.org, Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH V6 0/2] riscv: Support qspinlock with generic headers

On 6/21/22 10:49, guoren@...nel.org wrote:
> From: Guo Ren <guoren@...ux.alibaba.com>
>
> Enable qspinlock and meet the requirements mentioned in a8ad07e5240c9
> ("asm-generic: qspinlock: Indicate the use of mixed-size atomics").
>
> RISC-V LR/SC pairs could provide a strong/weak forward guarantee that
> depends on micro-architecture. And RISC-V ISA spec has given out
> several limitations to let hardware support strict forward guarantee
> (RISC-V User ISA - 8.3 Eventual Success of Store-Conditional
> Instructions):
> We restricted the length of LR/SC loops to fit within 64 contiguous
> instruction bytes in the base ISA to avoid undue restrictions on
> instruction cache and TLB size and associativity. Similarly, we

Does the 64 contiguous bytes need to be cacheline aligned?

Regards,
Longman