linux-kernel - Re: [PATCH V6 0/2] riscv: Support qspinlock with generic headers

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Message-ID: <CAJF2gTT4Q3HLabXPgACOmd-Z58LsD-77ga74pzgUT2scr+ydRA@mail.gmail.com>
Date:   Wed, 22 Jun 2022 09:51:35 +0800
From:   Guo Ren <guoren@...nel.org>
To:     Waiman Long <longman@...hat.com>
Cc:     Palmer Dabbelt <palmer@...osinc.com>,
        Arnd Bergmann <arnd@...db.de>,
        Peter Zijlstra <peterz@...radead.org>,
        Boqun Feng <boqun.feng@...il.com>, Conor.Dooley@...rochip.com,
        Huacai Chen <chenhuacai@...ngson.cn>,
        Xuerui Wang <kernel@...0n.name>, hev <r@....cc>,
        Stafford Horne <shorne@...il.com>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        linux-arch <linux-arch@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH V6 0/2] riscv: Support qspinlock with generic headers

On Tue, Jun 21, 2022 at 11:08 PM Waiman Long <longman@...hat.com> wrote:
>
> On 6/21/22 10:49, guoren@...nel.org wrote:
> > From: Guo Ren <guoren@...ux.alibaba.com>
> >
> > Enable qspinlock and meet the requirements mentioned in a8ad07e5240c9
> > ("asm-generic: qspinlock: Indicate the use of mixed-size atomics").
> >
> > RISC-V LR/SC pairs could provide a strong/weak forward guarantee that
> > depends on micro-architecture. And RISC-V ISA spec has given out
> > several limitations to let hardware support strict forward guarantee
> > (RISC-V User ISA - 8.3 Eventual Success of Store-Conditional
> > Instructions):
> > We restricted the length of LR/SC loops to fit within 64 contiguous
> > instruction bytes in the base ISA to avoid undue restrictions on
> > instruction cache and TLB size and associativity. Similarly, we
>
> Does the 64 contiguous bytes need to be cacheline aligned?
No, they are instructions, and the IFU & issue units would guarantee
that. The programmer needn't worry about that.

>
> Regards,
> Longman
>


-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/