linux-kernel - Re: [PATCH v6 16/16] arm64: dts: mediatek: Add infra #reset-cells property for MT8195

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Message-ID: <3a587e20-f991-adf8-fe4e-a09caa1e14c7@gmail.com>
Date:   Wed, 22 Jun 2022 13:08:05 +0200
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     Rex-BC Chen <rex-bc.chen@...iatek.com>, mturquette@...libre.com,
        sboyd@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org
Cc:     p.zabel@...gutronix.de, angelogioacchino.delregno@...labora.com,
        chun-jie.chen@...iatek.com, wenst@...omium.org,
        runyang.chen@...iatek.com, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, linux-clk@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-mediatek@...ts.infradead.org,
        Project_Global_Chrome_Upstream_Group@...iatek.com
Subject: Re: [PATCH v6 16/16] arm64: dts: mediatek: Add infra #reset-cells
 property for MT8195



On 03/05/2022 11:38, Rex-BC Chen wrote:
> We will use mediatek clock reset as infracfg_ao reset instead of
> ti-syscon. To support this, remove property of ti reset and add
> property of #reset-cells for mediatek clock reset.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@...iatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>

My understanding is that using the old DTS with a newer kernel wouldn't 
introduce a regression, correct?

Applied, thanks!

> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 13 +------------
>   1 file changed, 1 insertion(+), 12 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index b57e620c2c72..8e5ac11b19f1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -10,7 +10,6 @@
>   #include <dt-bindings/interrupt-controller/irq.h>
>   #include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
> -#include <dt-bindings/reset/ti-syscon.h>
>   
>   / {
>   	compatible = "mediatek,mt8195";
> @@ -295,17 +294,7 @@
>   			compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
>   			reg = <0 0x10001000 0 0x1000>;
>   			#clock-cells = <1>;
> -
> -			infracfg_rst: reset-controller {
> -				compatible = "ti,syscon-reset";
> -				#reset-cells = <1>;
> -				ti,reset-bits = <
> -					0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
> -					0x120 0  0x124 0  0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> -					0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
> -					0x150 5  0x154 5  0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
> -				>;
> -			};
> +			#reset-cells = <1>;
>   		};
>   
>   		pericfg: syscon@...03000 {