linux-kernel - Re: [PATCH V2 3/8] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Thu, 23 Jun 2022 23:05:35 -0500
From:   Bjorn Andersson <bjorn.andersson@...aro.org>
To:     Sricharan R <quic_srichara@...cinc.com>
Cc:     agross@...nel.org, robh+dt@...nel.org,
        krzysztof.kozlowski+dt@...aro.org, mturquette@...libre.com,
        sboyd@...nel.org, linus.walleij@...aro.org,
        catalin.marinas@....com, p.zabel@...gutronix.de,
        quic_varada@...cinc.com, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-gpio@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH V2 3/8] clk: qcom: Add Global Clock controller (GCC)
 driver for IPQ5018

On Tue 21 Jun 11:11 CDT 2022, Sricharan R wrote:
> diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c
[..]
> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
> +	{ .fw_name = "xo", .name = "xo", },

Please replace .fw_name with .index based lookup, in line with what was
done in gcc-sc8280xp.c recently.

There's no reason to include global name lookup (.name) in new drivers,
so please omit this part.

> +	{ .fw_name = "gpll0", .name = "gpll0", },
> +	{ .fw_name = "gpll0_out_main_div2", .name = "gpll0_out_main_div2", },
> +};
> +
[..]
> +static struct clk_alpha_pll gpll0_main = {
> +	.offset = 0x21000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.clkr = {
> +		.enable_reg = 0x0b000,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gpll0_main",
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "xo",
> +				.name = "xo",

Are you referring to the board XO here, or the CXO pin on the SoC? On
many platforms these are not the same...

Please omit the .name here as well and as this is used a few times,
please create a struct clk_parent_data for this parent.

> +			},
> +			.num_parents = 1,
> +			.ops = &clk_alpha_pll_stromer_ops,
> +			.flags = CLK_IS_CRITICAL,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor gpll0_out_main_div2 = {
> +	.mult = 1,
> +	.div = 2,
> +	.hw.init = &(struct clk_init_data){
> +		.name = "gpll0_out_main_div2",
> +		.parent_data = &(const struct clk_parent_data){

It would be nice to have a space inbetween ) and { in all these.

> +			.fw_name = "gpll0_main",
> +			.name = "gpll0_main",
> +		},
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
[..]
> +static struct clk_branch gcc_gephy_tx_clk = {
> +	.halt_reg = 0x56014,
> +	.halt_check = BRANCH_HALT_DELAY,
> +	.clkr = {
> +		.enable_reg = 0x56014,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data){
> +			.name = "gcc_gephy_tx_clk",
> +			.parent_data = &(const struct clk_parent_data){
> +				.fw_name = "gmac0_tx_div_clk_src",
> +				.name = "gmac0_tx_div_clk_src",
> +			},

This parent_data is repeated multiple times, but more importantly it's
not an external clock, so you should use .parent_hw instead of
.parent_data.

Please review the parent for all your clocks.

Regards,
Bjorn