linux-kernel - Re: [PATCH v4 3/5] perf arch events: riscv arch std event files

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Message-ID: <20220625083253.61b3e0db@redslave.neermore.group>
Date:   Sat, 25 Jun 2022 08:32:53 +0300
From:   Nikita Shubin <nikita.shubin@...uefel.me>
To:     Atish Patra <atishp@...shpatra.org>
Cc:     Anup Patel <anup@...infault.org>,
        João Mário Domingos 
        <joao.mario@...nico.ulisboa.pt>, linux <linux@...ro.com>,
        Nikita Shubin <n.shubin@...ro.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...nel.org>,
        Namhyung Kim <namhyung@...nel.org>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        "linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>,
        linux-perf-users@...r.kernel.org,
        linux-riscv <linux-riscv@...ts.infradead.org>
Subject: Re: [PATCH v4 3/5] perf arch events: riscv arch std event files

Hello Atish!

On Fri, 24 Jun 2022 10:01:07 -0700
Atish Patra <atishp@...shpatra.org> wrote:

> On Fri, Jun 24, 2022 at 9:01 AM Nikita Shubin
> <nikita.shubin@...uefel.me> wrote:
> >
> > From: Nikita Shubin <n.shubin@...ro.com>
> >
> > cycles, time and instret counters are defined by RISC-V privileged
> > spec and they should be available on any RISC-V implementation,
> > epose them to arch std event files, so they can be reused by
> > particular PMU bindings.
> >
> > Derived-from-code-by: João Mário Domingos
> > <joao.mario@...nico.ulisboa.pt> Signed-off-by: Nikita Shubin
> > <n.shubin@...ro.com>  
> 
> Why do we need this ? The PMU driver already parses the standard perf
> events. So you can pass -e cycles -e instructions.
> 
> Even though time is described as a counter and accessibility
> controlled by mcounteren, you can not start/stop it (no bit in
> mcountinhibit).
> Thus, it can't be used from perf.

My first thought was that we can use cycle, time, instret on any RISC-V
platform even without any bindings, but as you pointed out it's
indeed useless.

I'll drop this one.

> 
> > ---
> >  .../pmu-events/arch/riscv/riscv-generic.json  | 20
> > +++++++++++++++++++ 1 file changed, 20 insertions(+)
> >  create mode 100644
> > tools/perf/pmu-events/arch/riscv/riscv-generic.json
> >
> > diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json
> > b/tools/perf/pmu-events/arch/riscv/riscv-generic.json new file mode
> > 100644 index 000000000000..a7ffbe87a0f7
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
> > @@ -0,0 +1,20 @@
> > +[
> > +  {
> > +    "PublicDescription": "CPU Cycles",
> > +    "EventCode": "0x00",
> > +    "EventName": "riscv_cycles",
> > +    "BriefDescription": "CPU cycles RISC-V generic counter"
> > +  },
> > +  {
> > +    "PublicDescription": "CPU Time",
> > +    "EventCode": "0x01",
> > +    "EventName": "riscv_time",
> > +    "BriefDescription": "CPU time RISC-V generic counter"
> > +  },
> > +  {
> > +    "PublicDescription": "CPU Instructions",
> > +    "EventCode": "0x02",
> > +    "EventName": "riscv_instret",
> > +    "BriefDescription": "CPU retired instructions RISC-V generic
> > counter"
> > +  }
> > +]
> > --
> > 2.35.1
> >  
> 
>