linux-kernel - Re: [PATCH v3 7/7] clk: mediatek: Add MediaTek Helio X10 MT6795 clock drivers

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Date:   Sat, 25 Jun 2022 08:07:47 +0800
From:   Miles Chen <miles.chen@...iatek.com>
To:     <angelogioacchino.delregno@...labora.com>
CC:     <bgolaszewski@...libre.com>, <chun-jie.chen@...iatek.com>,
        <ck.hu@...iatek.com>, <devicetree@...r.kernel.org>,
        <fparent@...libre.com>, <ikjn@...omium.org>,
        <jason-jh.lin@...iatek.com>, <kernel@...labora.com>,
        <konrad.dybcio@...ainline.org>,
        <krzysztof.kozlowski+dt@...aro.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-mediatek@...ts.infradead.org>,
        <marijn.suijten@...ainline.org>, <martin.botka@...ainline.org>,
        <matthias.bgg@...il.com>, <miles.chen@...iatek.com>,
        <mturquette@...libre.com>, <p.zabel@...gutronix.de>,
        <paul.bouchara@...ainline.org>, <phone-devel@...r.kernel.org>,
        <rex-bc.chen@...iatek.com>, <robh+dt@...nel.org>,
        <sam.shih@...iatek.com>, <sboyd@...nel.org>,
        <tinghan.shen@...iatek.com>, <weiyi.lu@...iatek.com>,
        <wenst@...omium.org>, <y.oudjana@...tonmail.com>,
        <~postmarketos/upstreaming@...ts.sr.ht>
Subject: Re: [PATCH v3 7/7] clk: mediatek: Add MediaTek Helio X10 MT6795 clock drivers

Hi Angelo,

> Add the clock drivers for the entire clock tree of MediaTek Helio X10
> MT6795, including system clocks (apmixedsys, infracfg, pericfg, topckgen)
> and multimedia clocks (mmsys, mfg, vdecsys, vencsys).
> 
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> Reviewed-by: Matthias Brugger <matthias.bgg@...il.com>
> ---
>  drivers/clk/mediatek/Kconfig                 |  37 ++
>  drivers/clk/mediatek/Makefile                |   6 +
>  drivers/clk/mediatek/clk-mt6795-apmixedsys.c | 157 +++++
>  drivers/clk/mediatek/clk-mt6795-infracfg.c   | 148 +++++
>  drivers/clk/mediatek/clk-mt6795-mfg.c        |  50 ++
>  drivers/clk/mediatek/clk-mt6795-mm.c         | 106 ++++
>  drivers/clk/mediatek/clk-mt6795-pericfg.c    | 160 +++++
>  drivers/clk/mediatek/clk-mt6795-topckgen.c   | 610 +++++++++++++++++++
>  drivers/clk/mediatek/clk-mt6795-vdecsys.c    |  55 ++
>  drivers/clk/mediatek/clk-mt6795-vencsys.c    |  50 ++
>  10 files changed, 1379 insertions(+)
>  create mode 100644 drivers/clk/mediatek/clk-mt6795-apmixedsys.c
>  create mode 100644 drivers/clk/mediatek/clk-mt6795-infracfg.c
>  create mode 100644 drivers/clk/mediatek/clk-mt6795-mfg.c
>  create mode 100644 drivers/clk/mediatek/clk-mt6795-mm.c
>  create mode 100644 drivers/clk/mediatek/clk-mt6795-pericfg.c
>  create mode 100644 drivers/clk/mediatek/clk-mt6795-topckgen.c
>  create mode 100644 drivers/clk/mediatek/clk-mt6795-vdecsys.c
>  create mode 100644 drivers/clk/mediatek/clk-mt6795-vencsys.c
> 
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index d5936cfb3bee..da8142dff3c3 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -259,6 +259,43 @@ config COMMON_CLK_MT6779_AUDSYS
>  	help
>  	  This driver supports Mediatek MT6779 audsys clocks.
>  
> +config COMMON_CLK_MT6795
> +	tristate "Clock driver for MediaTek MT6795"
> +	depends on ARCH_MEDIATEK || COMPILE_TEST
> +	select COMMON_CLK_MEDIATEK
> +	default ARCH_MEDIATEK
> +	help
> +	  This driver supports MediaTek MT6795 basic clocks and clocks
> +	  required for various peripherals found on MediaTek.
> +
> +config COMMON_CLK_MT6795_MFGCFG
> +	tristate "Clock driver for MediaTek MT6795 mfgcfg"
> +	depends on COMMON_CLK_MT6795
> +	default COMMON_CLK_MT6795
> +	help
> +	  This driver supports MediaTek MT6795 mfgcfg clocks.
> +
> +config COMMON_CLK_MT6795_MMSYS
> +       tristate "Clock driver for MediaTek MT6795 mmsys"

snip...

> +	{ /* sentinel */ }
> +};
> +
> +static int clk_mt6795_infracfg_probe(struct platform_device *pdev)
> +{
> +	struct clk_hw_onecell_data *clk_data;
> +	struct device_node *node = pdev->dev.of_node;
> +	void __iomem *base;
> +	int ret;
> +
> +	base = devm_platform_ioremap_resource(pdev, 0);
> +	if (IS_ERR(base))
> +		return PTR_ERR(base);
> +
> +	clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
> +	if (!clk_data)
> +		return -ENOMEM;
> +
> +	ret = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
> +	if (ret)
> +		goto free_clk_data;
> +
> +	ret = mtk_clk_register_gates(node, infra_gates, ARRAY_SIZE(infra_gates), clk_data);
> +	if (ret)
> +		goto free_clk_data;

While checking the error path, I learned that
mtk_register_reset_controller_with_dev uses devm_reset_controller_register and it will
be unregister the reset automatically if probe failed.

Thanks for this patch!

Reviewed-by: Miles Chen <miles.chen@...iatek.com> 


thanks,
Miles

> +
> +	ret = mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
> +	if (ret)
> +		goto unregister_gates;
> +
> +	ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> +	if (ret)
> +		goto unregister_cpumuxes;
> +
> +	return 0;
> +
> +unregister_cpumuxes:
> +	mtk_clk_unregister_cpumuxes(cpu_muxes, ARRAY_SIZE(cpu_muxes), clk_data);
> +unregister_gates:
> +	mtk_clk_unregister_gates(infra_gates, ARRAY_SIZE(infra_gates), clk_data);
> +free_clk_data:
> +	mtk_free_clk_data(clk_data);
> +	return ret;
> +}
> +
> +static int clk_mt6795_infracfg_remove(struct platform_device *pdev)
> +{