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Message-ID: <HK0PR06MB32025ACEE605D1016DD3B99D80BB9@HK0PR06MB3202.apcprd06.prod.outlook.com>
Date: Wed, 29 Jun 2022 07:59:15 +0000
From: Neal Liu <neal_liu@...eedtech.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Corentin Labbe <clabbe.montjoie@...il.com>,
Christophe JAILLET <christophe.jaillet@...adoo.fr>,
Randy Dunlap <rdunlap@...radead.org>,
Herbert Xu <herbert@...dor.apana.org.au>,
"David S . Miller" <davem@...emloft.net>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Joel Stanley <joel@....id.au>,
Andrew Jeffery <andrew@...id.au>,
Dhananjay Phadke <dhphadke@...rosoft.com>,
Johnny Huang <johnny_huang@...eedtech.com>
CC: "linux-aspeed@...ts.ozlabs.org" <linux-aspeed@...ts.ozlabs.org>,
"linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
BMC-SW <BMC-SW@...eedtech.com>
Subject: RE: [PATCH v5 2/5] dt-bindings: clock: Add AST2500/AST2600 HACE reset
definition
> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Sent: Wednesday, June 29, 2022 1:58 PM
> To: Neal Liu <neal_liu@...eedtech.com>; Corentin Labbe
> <clabbe.montjoie@...il.com>; Christophe JAILLET
> <christophe.jaillet@...adoo.fr>; Randy Dunlap <rdunlap@...radead.org>;
> Herbert Xu <herbert@...dor.apana.org.au>; David S . Miller
> <davem@...emloft.net>; Rob Herring <robh+dt@...nel.org>; Krzysztof
> Kozlowski <krzysztof.kozlowski+dt@...aro.org>; Joel Stanley <joel@....id.au>;
> Andrew Jeffery <andrew@...id.au>; Dhananjay Phadke
> <dhphadke@...rosoft.com>; Johnny Huang
> <johnny_huang@...eedtech.com>
> Cc: linux-aspeed@...ts.ozlabs.org; linux-crypto@...r.kernel.org;
> devicetree@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> linux-kernel@...r.kernel.org; BMC-SW <BMC-SW@...eedtech.com>
> Subject: Re: [PATCH v5 2/5] dt-bindings: clock: Add AST2500/AST2600 HACE
> reset definition
>
> On 29/06/2022 05:20, Neal Liu wrote:
> > Add HACE reset bit definition for AST2500/AST2600.
> >
> > Signed-off-by: Neal Liu <neal_liu@...eedtech.com>
> > Signed-off-by: Johnny Huang <johnny_huang@...eedtech.com>
> > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> > ---
> > include/dt-bindings/clock/aspeed-clock.h | 3 ++-
> > include/dt-bindings/clock/ast2600-clock.h | 1 +
> > 2 files changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/include/dt-bindings/clock/aspeed-clock.h
> > b/include/dt-bindings/clock/aspeed-clock.h
> > index 9ff4f6e4558c..6e040f7c3426 100644
> > --- a/include/dt-bindings/clock/aspeed-clock.h
> > +++ b/include/dt-bindings/clock/aspeed-clock.h
> > @@ -46,11 +46,12 @@
> > #define ASPEED_RESET_MCTP 1
> > #define ASPEED_RESET_ADC 2
> > #define ASPEED_RESET_JTAG_MASTER 3
> > -#define ASPEED_RESET_MIC 4
> > +#define ASPEED_RESET_HACE 4
>
> I did not ack such change. This is a significant change from previous version,
> invalidating my previous ack.
>
> This breaks the ABI, so NAK without proper explanation why ABI break is
> accepted.
I changed the original define (MIC) into different value (see below diff), and add a new define for HACE.
How does that break the ABI? I'll be appreciated if you can explain it more details.
And sorry for not remove ack with new change.
>
> > #define ASPEED_RESET_PWM 5
> > #define ASPEED_RESET_PECI 6
> > #define ASPEED_RESET_I2C 7
> > #define ASPEED_RESET_AHB 8
> > #define ASPEED_RESET_CRT1 9
> > +#define ASPEED_RESET_MIC 18
> >
> > #endif
> > diff --git a/include/dt-bindings/clock/ast2600-clock.h
> > b/include/dt-bindings/clock/ast2600-clock.h
> > index 62b9520a00fd..d8b0db2f7a7d 100644
> > --- a/include/dt-bindings/clock/ast2600-clock.h
> > +++ b/include/dt-bindings/clock/ast2600-clock.h
> > @@ -111,6 +111,7 @@
> > #define ASPEED_RESET_PCIE_RC_O 19
> > #define ASPEED_RESET_PCIE_RC_OEN 18
> > #define ASPEED_RESET_PCI_DP 5
> > +#define ASPEED_RESET_HACE 4
> > #define ASPEED_RESET_AHB 1
> > #define ASPEED_RESET_SDRAM 0
> >
>
>
> Best regards,
> Krzysztof
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