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Message-ID: <20220701205444.GA1511232-robh@kernel.org>
Date: Fri, 1 Jul 2022 14:54:44 -0600
From: Rob Herring <robh@...nel.org>
To: Shengjiu Wang <shengjiu.wang@....com>
Cc: Xiubo.Lee@...il.com, nicoleotsuka@...il.com,
shengjiu.wang@...il.com, linux-kernel@...r.kernel.org,
lgirdwood@...il.com, tiwai@...e.com, devicetree@...r.kernel.org,
krzk+dt@...nel.org, perex@...ex.cz, linuxppc-dev@...ts.ozlabs.org,
festevam@...il.com, alsa-devel@...a-project.org,
broonie@...nel.org, robh+dt@...nel.org
Subject: Re: [PATCH v2 5/6] ASoC: dt-bindings: fsl_spdif: Add two PLL clock
source
On Fri, 01 Jul 2022 17:32:40 +0800, Shengjiu Wang wrote:
> Add two PLL clock source, they are the parent clocks of root clock
> one is for 8kHz series rates, another one is for 11kHz series rates.
> They are optional clocks, if there are such clocks, then driver
> can switch between them for supporting more accurate rates.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@....com>
> ---
> Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 ++++
> 1 file changed, 4 insertions(+)
>
Acked-by: Rob Herring <robh@...nel.org>
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