linux-kernel - Re: [PATCH v2 6/6] ASoC: dt-bindings: fsl-sai: Add two PLL clock source

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Message-ID: <20220701205452.GA1511590-robh@kernel.org>
Date:   Fri, 1 Jul 2022 14:54:52 -0600
From:   Rob Herring <robh@...nel.org>
To:     Shengjiu Wang <shengjiu.wang@....com>
Cc:     Xiubo.Lee@...il.com, perex@...ex.cz, festevam@...il.com,
        shengjiu.wang@...il.com, lgirdwood@...il.com,
        devicetree@...r.kernel.org, tiwai@...e.com,
        linuxppc-dev@...ts.ozlabs.org, nicoleotsuka@...il.com,
        linux-kernel@...r.kernel.org, alsa-devel@...a-project.org,
        robh+dt@...nel.org, krzk+dt@...nel.org, broonie@...nel.org
Subject: Re: [PATCH v2 6/6] ASoC: dt-bindings: fsl-sai: Add two PLL clock
 source

On Fri, 01 Jul 2022 17:32:41 +0800, Shengjiu Wang wrote:
> Add two PLL clock source, they are the parent clocks of root clock
> one is for 8kHz series rates, another one is for 11kHz series rates.
> They are optional clocks, if there are such clocks, then driver
> can switch between them for supporting more accurate rates.
> 
> Signed-off-by: Shengjiu Wang <shengjiu.wang@....com>
> ---
>  Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 +++
>  1 file changed, 3 insertions(+)
> 

Acked-by: Rob Herring <robh@...nel.org>