linux-kernel - Re: [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix T-HEAD PLIC edge flow

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Date:   Fri, 01 Jul 2022 15:28:48 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     Samuel Holland <samuel@...lland.org>
Cc:     Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
        Prabhakar <prabhakar.csengg@...il.com>,
        Sagar Kadam <sagar.kadam@...ive.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Guo Ren <guoren@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        linux-renesas-soc@...r.kernel.org,
        Biju Das <biju.das.jz@...renesas.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v3 0/4] Add PLIC support for Renesas RZ/Five SoC / Fix
 T-HEAD PLIC edge flow

On 2022-06-30 11:02, Samuel Holland wrote:
> This patch series adds PLIC support for Renesas RZ/Five SoC.
> 
> Since the T-HEAD C900 PLIC has the same behavior, it also applies the
> fix for that variant.
> 
> This series is an update of v2 of the RZ/Five series[0], and replaces
> the separate T-HEAD series[1].
> 
> [0]:
> https://lore.kernel.org/linux-riscv/20220626004326.8548-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> [1]:
> https://lore.kernel.org/linux-riscv/20220627051257.38543-1-samuel@sholland.org/
> 
> Changes in v3:
>  - Add a more detailed explanation for why #interrupt-cells differs
>  - Add andestech,nceplic100 as a fallback compatible
>  - Separate the conditional part of the binding into two blocks (one 
> for
>    the PLIC implementation and the other for the SoC integration)
>  - Use a quirk bit for selecting the flow instead of a variant ID
>  - Use the andestech,nceplic100 compatible to select the new behavior
>  - Use handle_edge_irq instead of handle_fasteoi_ack_irq so .irq_ack
>    always gets called
>  - Do not set the handler name, as RISC-V selects 
> GENERIC_IRQ_SHOW_LEVEL
>  - Use the same name for plic_edge_chip as plic_chip
> 
> Changes in v2:
>  - Fixed review comments pointed by Marc and Krzysztof.
> 
> Changes in v1:
>  - Fixed review comments pointed by Rob and Geert.
>  - Changed implementation for EDGE interrupt handling on Renesas 
> RZ/Five
>    SoC.
> 
> Lad Prabhakar (2):
>   dt-bindings: interrupt-controller: sifive,plic: Document Renesas
>     RZ/Five SoC
>   irqchip/sifive-plic: Add support for Renesas RZ/Five SoC
> 
> Samuel Holland (2):
>   dt-bindings: interrupt-controller: Require trigger type for T-HEAD
>     PLIC
>   irqchip/sifive-plic: Fix T-HEAD PLIC edge trigger handling
> 
>  .../sifive,plic-1.0.0.yaml                    | 65 +++++++++++++--
>  drivers/irqchip/irq-sifive-plic.c             | 80 +++++++++++++++++--
>  2 files changed, 135 insertions(+), 10 deletions(-)

I'm going to provisionally queue this into -next so that it
can get some testing. I'd still want the DT changes to be
Ack'ed before the next merge window though.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...