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Message-ID: <e3b344e7-4100-e0d4-0dcd-aeef4893ad43@linaro.org>
Date: Tue, 5 Jul 2022 15:42:08 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
To: Johan Hovold <johan+linaro@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>
Cc: Andy Gross <agross@...nel.org>, Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 01/14] arm64: dts: qcom: sc7280: drop PCIe PHY clock index
On 05/07/2022 14:40, Johan Hovold wrote:
> The QMP PCIe PHY provides a single clock so drop the redundant clock
> index.
>
> Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
Hmm. After checking the source code, the clocks entry of the phy@...e000
node also needs to be fixed.
And also maybe:
Fixes: bd7d507935ca ("arm64: dts: qcom: sc7280: Add pcie clock support")
Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related
nodes")
> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index e66fc67de206..b0ae2dbba50f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -818,7 +818,7 @@ gcc: clock-controller@...000 {
> reg = <0 0x00100000 0 0x1f0000>;
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> - <0>, <&pcie1_lane 0>,
> + <0>, <&pcie1_lane>,
> <0>, <0>, <0>, <0>;
> clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> "pcie_0_pipe_clk", "pcie_1_pipe_clk",
> @@ -2110,7 +2110,7 @@ pcie1_lane: phy@...e200 {
> clock-names = "pipe0";
>
> #phy-cells = <0>;
> - #clock-cells = <1>;
> + #clock-cells = <0>;
> clock-output-names = "pcie_1_pipe_clk";
> };
> };
--
With best wishes
Dmitry
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