linux-kernel - Re: [PATCH v6 2/4] dt-bindings: riscv: document cbom-block-size

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAJF2gTSCpixjAqPROP-vUuTwaiacjPsSQxiiLPi4y=XhXqELxQ@mail.gmail.com>
Date:   Wed, 6 Jul 2022 07:56:51 +0800
From:   Guo Ren <guoren@...nel.org>
To:     Heiko Stuebner <heiko@...ech.de>
Cc:     Palmer Dabbelt <palmer@...belt.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Wei Fu <wefu@...hat.com>,
        Christoph Muellner <cmuellner@...ux.com>,
        Philipp Tomsich <philipp.tomsich@...ll.eu>,
        Christoph Hellwig <hch@....de>,
        Samuel Holland <samuel@...lland.org>,
        Atish Patra <atishp@...shpatra.org>,
        Anup Patel <anup@...infault.org>,
        Nick Kossifidis <mick@....forth.gr>,
        Rob Herring <robh+dt@...nel.org>, krzk+dt@...nel.org,
        devicetree <devicetree@...r.kernel.org>,
        Drew Fustini <drew@...gleboard.org>,
        Randy Dunlap <rdunlap@...radead.org>,
        Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v6 2/4] dt-bindings: riscv: document cbom-block-size

Reviewed-by: Guo Ren <guoren@...nel.org>

On Wed, Jul 6, 2022 at 6:47 AM Heiko Stuebner <heiko@...ech.de> wrote:
>
> The Zicbom operates on a block-size defined for the cpu-core,
> which does not necessarily match other cache-sizes used.
>
> So add the necessary property for the system to know the core's
> block-size.
>
> Signed-off-by: Heiko Stuebner <heiko@...ech.de>
> Reviewed-by: Anup Patel <anup@...infault.org>
> Acked-by: Rob Herring <robh@...nel.org>
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index d632ac76532e..873dd12f6e89 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -63,6 +63,11 @@ properties:
>        - riscv,sv48
>        - riscv,none
>
> +  riscv,cbom-block-size:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    description:
> +      The blocksize in bytes for the Zicbom cache operations.
> +
>    riscv,isa:
>      description:
>        Identifies the specific RISC-V instruction set architecture
> --
> 2.35.1
>


-- 
Best Regards
 Guo Ren