linux-kernel - Re: [PATCH v4 2/2] PCI: qcom: Move all DBI register accesses after phy_power

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Message-ID: <62c8afaa.1c69fb81.2a871.00ca@mx.google.com>
Date:   Sat, 9 Jul 2022 00:28:56 +0200
From:   Christian Marangi <ansuelsmth@...il.com>
To:     Bjorn Helgaas <helgaas@...nel.org>
Cc:     Robert Marko <robimarko@...il.com>,
        Stanimir Varbanov <svarbanov@...sol.com>,
        Andy Gross <agross@...nel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        lpieralisi@...nel.org, Rob Herring <robh@...nel.org>, kw@...ux.com,
        Bjorn Helgaas <bhelgaas@...gle.com>, p.zabel@...gutronix.de,
        jingoohan1@...il.com, linux-pci@...r.kernel.org,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        open list <linux-kernel@...r.kernel.org>,
        johan+linaro@...nel.org,
        Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
Subject: Re: [PATCH v4 2/2] PCI: qcom: Move all DBI register accesses after
 phy_power_on()

On Fri, Jul 08, 2022 at 03:11:25PM -0500, Bjorn Helgaas wrote:
> On Fri, Jul 08, 2022 at 09:22:09PM +0200, Christian Marangi wrote:
> > On Fri, Jul 08, 2022 at 02:17:09PM -0500, Bjorn Helgaas wrote:
> > > On Fri, Jul 08, 2022 at 07:02:48PM +0200, Christian Marangi wrote:
> > > > On Fri, Jul 08, 2022 at 06:47:57PM +0200, Christian Marangi wrote:
> > > > > On Fri, Jul 08, 2022 at 06:39:37PM +0200, Robert Marko wrote:
> > > > > > On Thu, 7 Jul 2022 at 21:41, Bjorn Helgaas <helgaas@...nel.org> wrote:
> > > > > > > On Fri, Jun 24, 2022 at 12:44:20PM +0200, Robert Marko wrote:
> > > > > > > > IPQ8074 requires the PHY to be powered on before accessing DBI registers.
> > > > > > > > It's not clear whether other variants have the same dependency, but there
> > > > > > > > seems to be no reason for them to be different, so move all the DBI
> > > > > > > > accesses from .init() to .post_init() so they are all after phy_power_on().
> > > > > > > >
> > > > > > > > Signed-off-by: Robert Marko <robimarko@...il.com>
> > > > > > >
> > > > > > > Would any of the qcom driver folks care to review and ack this?
> > > > > > > Stanimir, Andy, Bjorn A (from get_maintainer.pl)?
> > > > > 
> > > > > Hi Bjorn,
> > > > > I tested this on ipq806x and the current patch cause regression as pci
> > > > > doesn't work anymore...
> > > > > This is a before the patch [1] and this is an after [2].
> > > > > 
> > > > > As you notice the main problem here is
> > > > > [    2.559962] qcom-pcie 1b700000.pci: Phy link never came up
> > > > > 
> > > > > The cause of this has already been bisected and actually it was a fixup
> > > > > pushed some time ago for 2_1_0.
> > > > > 
> > > > > Uboot can leave the pci in an underfined state and this
> > > > > writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
> > > > > is never called.
> > > > > 
> > > > > This is mandatory to a correct init and MUST be called before regulator
> > > > > enable and reset deassert or the "Phy link never came up" problem is
> > > > > triggered.
> > > > > 
> > > > > So to fix this we just have to have
> > > > > writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
> > > > > in qcom_pcie_init_2_1_0 right after the reset_contro_assert.
> > > > > 
> > > > > This command is also present in qcom_pcie_init_2_3_2 where the same
> > > > > exact reg is written so I assume 2_3_2 have the same regression and the
> > > > > write must be placed in init and can't be moved to post_init.
> > > > > 
> > > > > Feel free to tell me how to proceed if I should post an additional patch
> > > > > or you prefer Robi to respin this with the few lines reverted.
> > > > > 
> > > > > [1] https://gist.github.com/Ansuel/ec827319e585630356fc586273db6f0d
> > > > > [2] https://gist.github.com/Ansuel/63fbcab2681cd28a61ec52d7874fa30d
> > > > 
> > > > While testing this I notice something odd...
> > > > 
> > > > 2_4_2 prepare the pipe clock only AFTER PCIe clocks and reset are
> > > > enabled while in 2_1_0... That made me think there could be a problem
> > > > with the current code of 2_1_0... A quick change made me discover that
> > > > the problem is actually that we enable prepare_enable clock BEFORE the
> > > > value is written in PCIE20_PARF_PHY_CTRL.
> > > > 
> > > > By moving the clk_bulk_prepare_enable after the "enable PCIe clocks and
> > > > resets" make the pci work with the current change...
> > > > 
> > > > So it could be that the current changes are correct and it's really just
> > > > a bug in 2_1_0 enabling clock before writing the correct value...
> > > > 
> > > > Tell me how to proceed... think at this point a good idea would be to
> > > > create a separate patch and fix this for good.
> > > 
> > > Hmm, I think I made a mistake when I put this patch in the middle and
> > > applied other stuff on top of it.  I'd like to just postpone this
> > > patch while we work out these issues, but I think it's not completely
> > > trivial since it's in the middle.  I'll try to straighten this out
> > > next week.
> > 
> > From my discoveries it really seems just a bug in 2_1_0 with enabling
> > the phy clk BEFORE setting the require bit...
> > 
> > Moving the bulk_prepare_enable after the bit is set makes everything
> > works as it should... If you want I can send a patch as that is clearly
> > a bug and currenty we have a workaround in place...
> 
> That'd be great!  Since it's an actual bug fix, I think it would be
> good if it were a separate patch instead of doing in the middle of a
> patch that also does other things.
> 
> Bjorn

Just sent the small fix that will indirectly make this series work as it
should. 

-- 
	Ansuel