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Message-ID: <20220709080203.GL5063@thinkpad>
Date: Sat, 9 Jul 2022 13:32:03 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Johan Hovold <johan+linaro@...nel.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
Stanimir Varbanov <svarbanov@...sol.com>,
Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Dmitry Baryshkov <dmitry.baryshkov@...aro.org>,
linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 05/10] dt-bindings: PCI: qcom: Add SA8540P to binding
On Wed, Jun 29, 2022 at 04:09:55PM +0200, Johan Hovold wrote:
> SA8540P is a new platform related to SC8280XP but which uses a single
> host interrupt for MSI routing.
>
The newer chipsets are supposed to use 8 MSI's. How come this one uses only 1?
Thanks,
Mani
> Signed-off-by: Johan Hovold <johan+linaro@...nel.org>
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> index a039f6110322..e9a7c8c783e7 100644
> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
> @@ -25,6 +25,7 @@ properties:
> - qcom,pcie-ipq4019
> - qcom,pcie-ipq8074
> - qcom,pcie-qcs404
> + - qcom,pcie-sa8540p
> - qcom,pcie-sc7280
> - qcom,pcie-sc8180x
> - qcom,pcie-sc8280xp
> @@ -603,6 +604,7 @@ allOf:
> compatible:
> contains:
> enum:
> + - qcom,pcie-sa8540p
> - qcom,pcie-sc8280xp
> then:
> properties:
> @@ -720,6 +722,7 @@ allOf:
> - qcom,pcie-ipq8064
> - qcom,pcie-ipq8064-v2
> - qcom,pcie-ipq8074
> + - qcom,pcie-sa8540p
> - qcom,pcie-qcs404
> then:
> properties:
> --
> 2.35.1
>
--
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