linux-kernel - Re: [PATCH] spi: SPI_MICROCHIP_CORE should depend on SOC_MICROCHIP

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <f297d979-4e30-e882-f9da-2e6401123617@microchip.com>
Date:   Mon, 11 Jul 2022 10:46:00 +0000
From:   <Conor.Dooley@...rochip.com>
To:     <geert+renesas@...der.be>, <broonie@...nel.org>,
        <Daire.McNamara@...rochip.com>
CC:     <linux-spi@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] spi: SPI_MICROCHIP_CORE should depend on
 SOC_MICROCHIP_POLARFIRE

On 11/07/2022 11:33, Conor Dooley wrote:
> On 11/07/2022 09:45, Geert Uytterhoeven wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> The Microchip "hard" FPGA SPI controller is only present on Microchip
>> PolarFire SoCs.  Hence add a dependency on SOC_MICROCHIP_POLARFIRE, to
>> prevent asking the user about this driver when configuring a kernel
>> without Microchip PolarFire SoC support.
>>
>> Fixes: 9ac8d17694b66d54 ("spi: add support for microchip fpga spi controllers")
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@...der.be>
> 
> Until I get the "soft" version sorted, makes sense to me.
> Reviewed-by: Conor Dooley <conor.dooley@...rochip.com>

Actually, I was thinking about why the "soft" version would change
anything and I realised that this is not correct.

I rescind my R-b.

You can also use this on the HiFive Unleashed Expansion board via
chiplink:
https://raw.githubusercontent.com/polarfire-soc/polarfire-soc-documentation/master/boards/lc-mpfs-dev-kit/images/updated-lc-libero-design.png

I have never tried this so I forgot about it, but just as the PCI
root port is accessible, so is the SPI.

Sorry!