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Message-ID: <CAHp75Vfs8EH-rRn58cS692tZMRFmjFLv6=kB4oqVEGXi5R8BHQ@mail.gmail.com>
Date: Mon, 11 Jul 2022 21:47:53 +0200
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Horatiu Vultur <horatiu.vultur@...rochip.com>
Cc: "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Linus Walleij <linus.walleij@...aro.org>,
kavyasree.kotagiri@...rochip.com,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Colin Foster <colin.foster@...advantage.com>,
Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
Maxime Chevallier <maxime.chevallier@...tlin.com>,
Michael Walle <michael@...le.cc>
Subject: Re: [PATCH v3 1/2] pinctrl: ocelot: Fix pincfg for lan966x
On Mon, Jul 11, 2022 at 9:17 PM Horatiu Vultur
<horatiu.vultur@...rochip.com> wrote:
>
> The blamed commit introduce support for lan966x which use the same
> pinconf_ops as sparx5. The problem is that pinconf_ops is specific to
> sparx5. More precisely the offset of the bits in the pincfg register are
> different and also lan966x doesn't have support for
> PIN_CONFIG_INPUT_SCHMITT_ENABLE.
>
> Fix this by making pinconf_ops more generic such that it can be also
> used by lan966x. This is done by introducing 'ocelot_pincfg_data' which
> contains the offset and what is supported for each SOC.
Thanks for an update!
My comments below.
...
I believe introducing
struct ocelot_pincfg_data *opd = info->pincfg_data;
may allow to reduce LoCs...
> + *val = regcfg &
> + (info->pincfg_data->pd_bit |
> + info->pincfg_data->pu_bit);
...like here:
*val = regcfg & (opd->pd_bit | opd->pu_bit);
...
> + info->desc = devm_kmemdup(dev, &data->desc,
> + sizeof(struct pinctrl_desc), GFP_KERNEL);
sizeof(*info->desc)
and missed the NULL check.
...
> + info->pincfg_data = devm_kmemdup(dev, &data->pincfg_data,
> + sizeof(struct ocelot_match_data),
sizeof(*info->pincfg_data)
(isn't it a bug here?)
> + GFP_KERNEL);
and missed the NULL check.
--
With Best Regards,
Andy Shevchenko
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