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Message-ID: <CAHp75VdeZSP62qoOdQf=g4b7AheFd4=jNxfjMh-_T7Q1Zi=LbA@mail.gmail.com>
Date: Mon, 11 Jul 2022 21:51:20 +0200
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Horatiu Vultur <horatiu.vultur@...rochip.com>
Cc: "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Linus Walleij <linus.walleij@...aro.org>,
kavyasree.kotagiri@...rochip.com,
Alexandre Belloni <alexandre.belloni@...tlin.com>,
Colin Foster <colin.foster@...advantage.com>,
Microchip Linux Driver Support <UNGLinuxDriver@...rochip.com>,
Maxime Chevallier <maxime.chevallier@...tlin.com>,
Michael Walle <michael@...le.cc>
Subject: Re: [PATCH v3 2/2] pinctrl: ocelot: Fix pincfg
On Mon, Jul 11, 2022 at 9:17 PM Horatiu Vultur
<horatiu.vultur@...rochip.com> wrote:
>
> The blamed commit changed to use regmaps instead of __iomem. But it
> didn't update the register offsets to be at word offset, so it uses byte
> offset.
> Another issue with the same commit is that it has a limit of 32 registers
> which is incorrect. The sparx5 has 64 while lan966x has 77.
...
> -static struct regmap *ocelot_pinctrl_create_pincfg(struct platform_device *pdev)
> +static struct regmap *ocelot_pinctrl_create_pincfg(struct ocelot_pinctrl *info,
> + struct platform_device *pdev)
const?
And I would leave pdev to be the first parameter, if there are no
other functions that have them like this.
--
With Best Regards,
Andy Shevchenko
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